Skip to content

M
Motor_Control
Commit 17550fa0 by 刘大爷来也
Options

创建电机项目，新增加速，减速

parents
Showing with 8356 additions and 0 deletions
DebugConfig/PWM_STM32F103ZE_1.0.0.dbgconf 0 → 100644
// File: STM32F101_102_103_105_107.dbgconf
// Version: 1.0.0
// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <i> Reserved bits must be kept at reset value
// <o.30> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.29> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.28> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// <o.27> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
// <o.26> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
// <o.25> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
// <o.21> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
// <o.20> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.19> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.18> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
// <o.17> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
// <o.16> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.15> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.14> DBG_CAN1_STOP <i> Debug CAN1 stopped when Core is halted
// <o.13> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.12> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.11> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// <o.10> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
// <o.9> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
// <o.8> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
// <o.2> DBG_STANDBY <i> Debug standby mode
// <o.1> DBG_STOP <i> Debug stop mode
// <o.0> DBG_SLEEP <i> Debug sleep mode
// </h>
DbgMCU_CR = 0x00000007;
// <<< end of configuration section >>>
DebugConfig/Target_1_STM32F103ZE_1.0.0.dbgconf 0 → 100644
// File: STM32F101_102_103_105_107.dbgconf
// Version: 1.0.0
// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <i> Reserved bits must be kept at reset value
// <o.30> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.29> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.28> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// <o.27> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
// <o.26> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
// <o.25> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
// <o.21> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
// <o.20> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.19> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.18> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
// <o.17> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
// <o.16> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.15> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.14> DBG_CAN1_STOP <i> Debug CAN1 stopped when Core is halted
// <o.13> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.12> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.11> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// <o.10> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
// <o.9> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
// <o.8> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
// <o.2> DBG_STANDBY <i> Debug standby mode
// <o.1> DBG_STOP <i> Debug stop mode
// <o.0> DBG_SLEEP <i> Debug sleep mode
// </h>
DbgMCU_CR = 0x00000007;
// <<< end of configuration section >>>
Listings/MotorControl.map 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Listings/startup_stm32f10x_hd.lst 0 → 100644
ARM Macro Assembler Page 1
1 00000000 ;******************** (C) COPYRIGHT 2011 STMicroelectron
ics ********************
2 00000000 ;* File Name : startup_stm32f10x_hd.s
3 00000000 ;* Author : MCD Application Team
4 00000000 ;* Version : V3.5.1
5 00000000 ;* Date : 08-September-2021
6 00000000 ;* Description : STM32F10x High Density Devices v
ector table for MDK-ARM
7 00000000 ;* toolchain.
8 00000000 ;* This module performs:
9 00000000 ;* - Set the initial SP
10 00000000 ;* - Set the initial PC == Reset_Ha
ndler
11 00000000 ;* - Set the vector table entries w
ith the exceptions ISR address
12 00000000 ;* - Configure the clock system and
also configure the external
13 00000000 ;* SRAM mounted on STM3210E-EVAL
board to be used as data
14 00000000 ;* memory (optional, to be enable
d by user)
15 00000000 ;* - Branches to __main in the C li
brary (which eventually
16 00000000 ;* calls main()).
17 00000000 ;* After Reset the CortexM3 process
or is in Thread mode,
18 00000000 ;* priority is Privileged, and the
Stack is set to Main.
19 00000000 ;* <<< Use Configuration Wizard in Context Menu >>>
20 00000000 ;*******************************************************
************************
21 00000000 ;*
22 00000000 ;* Copyright (c) 2011 STMicroelectronics.
23 00000000 ;* All rights reserved.
24 00000000 ;*
25 00000000 ;* This software is licensed under terms that can be fou
nd in the LICENSE file
26 00000000 ;* in the root directory of this software component.
27 00000000 ;* If no LICENSE file comes with this software, it is pr
ovided AS-IS.
28 00000000 ;
29 00000000 ;*******************************************************
************************
30 00000000
31 00000000 ; Amount of memory (in bytes) allocated for Stack
32 00000000 ; Tailor this value to your application needs
33 00000000 ; <h> Stack Configuration
34 00000000 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
35 00000000 ; </h>
36 00000000
37 00000000 00000400
Stack_Size
EQU 0x00000400
38 00000000
39 00000000 AREA STACK, NOINIT, READWRITE, ALIGN
=3
40 00000000 Stack_Mem
SPACE Stack_Size
41 00000400 __initial_sp
ARM Macro Assembler Page 2
42 00000400
43 00000400 ; <h> Heap Configuration
44 00000400 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
45 00000400 ; </h>
46 00000400
47 00000400 00000200
Heap_Size
EQU 0x00000200
48 00000400
49 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN=
3
50 00000000 __heap_base
51 00000000 Heap_Mem
SPACE Heap_Size
52 00000200 __heap_limit
53 00000200
54 00000200 PRESERVE8
55 00000200 THUMB
56 00000200
57 00000200
58 00000200 ; Vector Table Mapped to Address 0 at Reset
59 00000200 AREA RESET, DATA, READONLY
60 00000000 EXPORT __Vectors
61 00000000 EXPORT __Vectors_End
62 00000000 EXPORT __Vectors_Size
63 00000000
64 00000000 00000000
__Vectors
DCD __initial_sp ; Top of Stack
65 00000004 00000000 DCD Reset_Handler ; Reset Handler
66 00000008 00000000 DCD NMI_Handler ; NMI Handler
67 0000000C 00000000 DCD HardFault_Handler ; Hard Fault
Handler
68 00000010 00000000 DCD MemManage_Handler
; MPU Fault Handler
69 00000014 00000000 DCD BusFault_Handler
; Bus Fault Handler
70 00000018 00000000 DCD UsageFault_Handler ; Usage Faul
t Handler
71 0000001C 00000000 DCD 0 ; Reserved
72 00000020 00000000 DCD 0 ; Reserved
73 00000024 00000000 DCD 0 ; Reserved
74 00000028 00000000 DCD 0 ; Reserved
75 0000002C 00000000 DCD SVC_Handler ; SVCall Handler
76 00000030 00000000 DCD DebugMon_Handler ; Debug Monito
r Handler
77 00000034 00000000 DCD 0 ; Reserved
78 00000038 00000000 DCD PendSV_Handler ; PendSV Handler
79 0000003C 00000000 DCD SysTick_Handler
; SysTick Handler
80 00000040
81 00000040 ; External Interrupts
82 00000040 00000000 DCD WWDG_IRQHandler
; Window Watchdog
83 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX
TI Line detect
ARM Macro Assembler Page 3
84 00000048 00000000 DCD TAMPER_IRQHandler ; Tamper
85 0000004C 00000000 DCD RTC_IRQHandler ; RTC
86 00000050 00000000 DCD FLASH_IRQHandler ; Flash
87 00000054 00000000 DCD RCC_IRQHandler ; RCC
88 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line 0
89 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line 1
90 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line 2
91 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line 3
92 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line 4
93 0000006C 00000000 DCD DMA1_Channel1_IRQHandler
; DMA1 Channel 1
94 00000070 00000000 DCD DMA1_Channel2_IRQHandler
; DMA1 Channel 2
95 00000074 00000000 DCD DMA1_Channel3_IRQHandler
; DMA1 Channel 3
96 00000078 00000000 DCD DMA1_Channel4_IRQHandler
; DMA1 Channel 4
97 0000007C 00000000 DCD DMA1_Channel5_IRQHandler
; DMA1 Channel 5
98 00000080 00000000 DCD DMA1_Channel6_IRQHandler
; DMA1 Channel 6
99 00000084 00000000 DCD DMA1_Channel7_IRQHandler
; DMA1 Channel 7
100 00000088 00000000 DCD ADC1_2_IRQHandler ; ADC1 & ADC2
101 0000008C 00000000 DCD USB_HP_CAN1_TX_IRQHandler ; USB
High Priority or C
AN1 TX
102 00000090 00000000 DCD USB_LP_CAN1_RX0_IRQHandler ; US
B Low Priority or
CAN1 RX0
103 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
104 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
105 0000009C 00000000 DCD EXTI9_5_IRQHandler
; EXTI Line 9..5
106 000000A0 00000000 DCD TIM1_BRK_IRQHandler
; TIM1 Break
107 000000A4 00000000 DCD TIM1_UP_IRQHandler
; TIM1 Update
108 000000A8 00000000 DCD TIM1_TRG_COM_IRQHandler ; TIM1
Trigger and Commuta
tion
109 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu
re Compare
110 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2
111 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3
112 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4
113 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event
114 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error
115 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event
116 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error
117 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1
118 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2
119 000000D4 00000000 DCD USART1_IRQHandler ; USART1
120 000000D8 00000000 DCD USART2_IRQHandler ; USART2
ARM Macro Assembler Page 4
121 000000DC 00000000 DCD USART3_IRQHandler ; USART3
122 000000E0 00000000 DCD EXTI15_10_IRQHandler
; EXTI Line 15..10
123 000000E4 00000000 DCD RTCAlarm_IRQHandler ; RTC Alarm
through EXTI Line
124 000000E8 00000000 DCD USBWakeUp_IRQHandler ; USB Wake
up from suspend
125 000000EC 00000000 DCD TIM8_BRK_IRQHandler
; TIM8 Break
126 000000F0 00000000 DCD TIM8_UP_IRQHandler
; TIM8 Update
127 000000F4 00000000 DCD TIM8_TRG_COM_IRQHandler ; TIM8
Trigger and Commuta
tion
128 000000F8 00000000 DCD TIM8_CC_IRQHandler ; TIM8 Captu
re Compare
129 000000FC 00000000 DCD ADC3_IRQHandler ; ADC3
130 00000100 00000000 DCD FSMC_IRQHandler ; FSMC
131 00000104 00000000 DCD SDIO_IRQHandler ; SDIO
132 00000108 00000000 DCD TIM5_IRQHandler ; TIM5
133 0000010C 00000000 DCD SPI3_IRQHandler ; SPI3
134 00000110 00000000 DCD UART4_IRQHandler ; UART4
135 00000114 00000000 DCD UART5_IRQHandler ; UART5
136 00000118 00000000 DCD TIM6_IRQHandler ; TIM6
137 0000011C 00000000 DCD TIM7_IRQHandler ; TIM7
138 00000120 00000000 DCD DMA2_Channel1_IRQHandler
; DMA2 Channel1
139 00000124 00000000 DCD DMA2_Channel2_IRQHandler
; DMA2 Channel2
140 00000128 00000000 DCD DMA2_Channel3_IRQHandler
; DMA2 Channel3
141 0000012C 00000000 DCD DMA2_Channel4_5_IRQHandler ; DM
A2 Channel4 & Chann
el5
142 00000130 __Vectors_End
143 00000130
144 00000130 00000130
__Vectors_Size
EQU __Vectors_End - __Vectors
145 00000130
146 00000130 AREA |.text|, CODE, READONLY
147 00000000
148 00000000 ; Reset handler
149 00000000 Reset_Handler
PROC
150 00000000 EXPORT Reset_Handler [WEAK
]
151 00000000 IMPORT __main
152 00000000 IMPORT SystemInit
153 00000000 4809 LDR R0, =SystemInit
154 00000002 4780 BLX R0
155 00000004 4809 LDR R0, =__main
156 00000006 4700 BX R0
157 00000008 ENDP
158 00000008
159 00000008 ; Dummy Exception Handlers (infinite loops which can be
modified)
160 00000008
161 00000008 NMI_Handler
ARM Macro Assembler Page 5
PROC
162 00000008 EXPORT NMI_Handler [WEA
K]
163 00000008 E7FE B .
164 0000000A ENDP
166 0000000A HardFault_Handler
PROC
167 0000000A EXPORT HardFault_Handler [WEA
K]
168 0000000A E7FE B .
169 0000000C ENDP
171 0000000C MemManage_Handler
PROC
172 0000000C EXPORT MemManage_Handler [WEA
K]
173 0000000C E7FE B .
174 0000000E ENDP
176 0000000E BusFault_Handler
PROC
177 0000000E EXPORT BusFault_Handler [WEA
K]
178 0000000E E7FE B .
179 00000010 ENDP
181 00000010 UsageFault_Handler
PROC
182 00000010 EXPORT UsageFault_Handler [WEA
K]
183 00000010 E7FE B .
184 00000012 ENDP
185 00000012 SVC_Handler
PROC
186 00000012 EXPORT SVC_Handler [WEA
K]
187 00000012 E7FE B .
188 00000014 ENDP
190 00000014 DebugMon_Handler
PROC
191 00000014 EXPORT DebugMon_Handler [WEA
K]
192 00000014 E7FE B .
193 00000016 ENDP
194 00000016 PendSV_Handler
PROC
195 00000016 EXPORT PendSV_Handler [WEA
K]
196 00000016 E7FE B .
197 00000018 ENDP
198 00000018 SysTick_Handler
PROC
199 00000018 EXPORT SysTick_Handler [WEA
K]
200 00000018 E7FE B .
201 0000001A ENDP
202 0000001A
203 0000001A Default_Handler
PROC
204 0000001A
205 0000001A EXPORT WWDG_IRQHandler [WEA
K]
ARM Macro Assembler Page 6
206 0000001A EXPORT PVD_IRQHandler [WEA
K]
207 0000001A EXPORT TAMPER_IRQHandler [WEA
K]
208 0000001A EXPORT RTC_IRQHandler [WEA
K]
209 0000001A EXPORT FLASH_IRQHandler [WEA
K]
210 0000001A EXPORT RCC_IRQHandler [WEA
K]
211 0000001A EXPORT EXTI0_IRQHandler [WEA
K]
212 0000001A EXPORT EXTI1_IRQHandler [WEA
K]
213 0000001A EXPORT EXTI2_IRQHandler [WEA
K]
214 0000001A EXPORT EXTI3_IRQHandler [WEA
K]
215 0000001A EXPORT EXTI4_IRQHandler [WEA
K]
216 0000001A EXPORT DMA1_Channel1_IRQHandler [WEA
K]
217 0000001A EXPORT DMA1_Channel2_IRQHandler [WEA
K]
218 0000001A EXPORT DMA1_Channel3_IRQHandler [WEA
K]
219 0000001A EXPORT DMA1_Channel4_IRQHandler [WEA
K]
220 0000001A EXPORT DMA1_Channel5_IRQHandler [WEA
K]
221 0000001A EXPORT DMA1_Channel6_IRQHandler [WEA
K]
222 0000001A EXPORT DMA1_Channel7_IRQHandler [WEA
K]
223 0000001A EXPORT ADC1_2_IRQHandler [WEA
K]
224 0000001A EXPORT USB_HP_CAN1_TX_IRQHandler [WEA
K]
225 0000001A EXPORT USB_LP_CAN1_RX0_IRQHandler [WEA
K]
226 0000001A EXPORT CAN1_RX1_IRQHandler [WEA
K]
227 0000001A EXPORT CAN1_SCE_IRQHandler [WEA
K]
228 0000001A EXPORT EXTI9_5_IRQHandler [WEA
K]
229 0000001A EXPORT TIM1_BRK_IRQHandler [WEA
K]
230 0000001A EXPORT TIM1_UP_IRQHandler [WEA
K]
231 0000001A EXPORT TIM1_TRG_COM_IRQHandler [WEA
K]
232 0000001A EXPORT TIM1_CC_IRQHandler [WEA
K]
233 0000001A EXPORT TIM2_IRQHandler [WEA
K]
234 0000001A EXPORT TIM3_IRQHandler [WEA
K]
235 0000001A EXPORT TIM4_IRQHandler [WEA
ARM Macro Assembler Page 7
K]
236 0000001A EXPORT I2C1_EV_IRQHandler [WEA
K]
237 0000001A EXPORT I2C1_ER_IRQHandler [WEA
K]
238 0000001A EXPORT I2C2_EV_IRQHandler [WEA
K]
239 0000001A EXPORT I2C2_ER_IRQHandler [WEA
K]
240 0000001A EXPORT SPI1_IRQHandler [WEA
K]
241 0000001A EXPORT SPI2_IRQHandler [WEA
K]
242 0000001A EXPORT USART1_IRQHandler [WEA
K]
243 0000001A EXPORT USART2_IRQHandler [WEA
K]
244 0000001A EXPORT USART3_IRQHandler [WEA
K]
245 0000001A EXPORT EXTI15_10_IRQHandler [WEA
K]
246 0000001A EXPORT RTCAlarm_IRQHandler [WEA
K]
247 0000001A EXPORT USBWakeUp_IRQHandler [WEA
K]
248 0000001A EXPORT TIM8_BRK_IRQHandler [WEA
K]
249 0000001A EXPORT TIM8_UP_IRQHandler [WEA
K]
250 0000001A EXPORT TIM8_TRG_COM_IRQHandler [WEA
K]
251 0000001A EXPORT TIM8_CC_IRQHandler [WEA
K]
252 0000001A EXPORT ADC3_IRQHandler [WEA
K]
253 0000001A EXPORT FSMC_IRQHandler [WEA
K]
254 0000001A EXPORT SDIO_IRQHandler [WEA
K]
255 0000001A EXPORT TIM5_IRQHandler [WEA
K]
256 0000001A EXPORT SPI3_IRQHandler [WEA
K]
257 0000001A EXPORT UART4_IRQHandler [WEA
K]
258 0000001A EXPORT UART5_IRQHandler [WEA
K]
259 0000001A EXPORT TIM6_IRQHandler [WEA
K]
260 0000001A EXPORT TIM7_IRQHandler [WEA
K]
261 0000001A EXPORT DMA2_Channel1_IRQHandler [WEA
K]
262 0000001A EXPORT DMA2_Channel2_IRQHandler [WEA
K]
263 0000001A EXPORT DMA2_Channel3_IRQHandler [WEA
K]
264 0000001A EXPORT DMA2_Channel4_5_IRQHandler [WEA
K]
ARM Macro Assembler Page 8
265 0000001A
266 0000001A WWDG_IRQHandler
267 0000001A PVD_IRQHandler
268 0000001A TAMPER_IRQHandler
269 0000001A RTC_IRQHandler
270 0000001A FLASH_IRQHandler
271 0000001A RCC_IRQHandler
272 0000001A EXTI0_IRQHandler
273 0000001A EXTI1_IRQHandler
274 0000001A EXTI2_IRQHandler
275 0000001A EXTI3_IRQHandler
276 0000001A EXTI4_IRQHandler
277 0000001A DMA1_Channel1_IRQHandler
278 0000001A DMA1_Channel2_IRQHandler
279 0000001A DMA1_Channel3_IRQHandler
280 0000001A DMA1_Channel4_IRQHandler
281 0000001A DMA1_Channel5_IRQHandler
282 0000001A DMA1_Channel6_IRQHandler
283 0000001A DMA1_Channel7_IRQHandler
284 0000001A ADC1_2_IRQHandler
285 0000001A USB_HP_CAN1_TX_IRQHandler
286 0000001A USB_LP_CAN1_RX0_IRQHandler
287 0000001A CAN1_RX1_IRQHandler
288 0000001A CAN1_SCE_IRQHandler
289 0000001A EXTI9_5_IRQHandler
290 0000001A TIM1_BRK_IRQHandler
291 0000001A TIM1_UP_IRQHandler
292 0000001A TIM1_TRG_COM_IRQHandler
293 0000001A TIM1_CC_IRQHandler
294 0000001A TIM2_IRQHandler
295 0000001A TIM3_IRQHandler
296 0000001A TIM4_IRQHandler
297 0000001A I2C1_EV_IRQHandler
298 0000001A I2C1_ER_IRQHandler
299 0000001A I2C2_EV_IRQHandler
300 0000001A I2C2_ER_IRQHandler
301 0000001A SPI1_IRQHandler
302 0000001A SPI2_IRQHandler
303 0000001A USART1_IRQHandler
304 0000001A USART2_IRQHandler
305 0000001A USART3_IRQHandler
306 0000001A EXTI15_10_IRQHandler
307 0000001A RTCAlarm_IRQHandler
308 0000001A USBWakeUp_IRQHandler
309 0000001A TIM8_BRK_IRQHandler
310 0000001A TIM8_UP_IRQHandler
311 0000001A TIM8_TRG_COM_IRQHandler
312 0000001A TIM8_CC_IRQHandler
313 0000001A ADC3_IRQHandler
314 0000001A FSMC_IRQHandler
315 0000001A SDIO_IRQHandler
316 0000001A TIM5_IRQHandler
317 0000001A SPI3_IRQHandler
318 0000001A UART4_IRQHandler
319 0000001A UART5_IRQHandler
320 0000001A TIM6_IRQHandler
321 0000001A TIM7_IRQHandler
322 0000001A DMA2_Channel1_IRQHandler
323 0000001A DMA2_Channel2_IRQHandler
ARM Macro Assembler Page 9
324 0000001A DMA2_Channel3_IRQHandler
325 0000001A DMA2_Channel4_5_IRQHandler
326 0000001A E7FE B .
327 0000001C
328 0000001C ENDP
329 0000001C
330 0000001C ALIGN
331 0000001C
332 0000001C ;*******************************************************
************************
333 0000001C ; User Stack and Heap initialization
334 0000001C ;*******************************************************
************************
335 0000001C IF :DEF:__MICROLIB
342 0000001C
343 0000001C IMPORT __use_two_region_memory
344 0000001C EXPORT __user_initial_stackheap
345 0000001C
346 0000001C __user_initial_stackheap
347 0000001C
348 0000001C 4804 LDR R0, = Heap_Mem
349 0000001E 4905 LDR R1, =(Stack_Mem + Stack_Size)
350 00000020 4A05 LDR R2, = (Heap_Mem + Heap_Size)
351 00000022 4B06 LDR R3, = Stack_Mem
352 00000024 4770 BX LR
353 00000026
354 00000026 00 00 ALIGN
355 00000028
356 00000028 ENDIF
357 00000028
358 00000028 END
00000000
00000000
00000000
00000400
00000200
00000000
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
ork --depend=.\objects\startup_stm32f10x_hd.d -o.\objects\startup_stm32f10x_hd.
o -ID:\Ƕʽ\mcu\Motor_Control\RTE -ID:\Ƕʽ\mcu\Motor_Control\RTE\Device\ST
M32F103ZE -IC:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1 -IC:\Keil_v5\ARM\PACK\
Keil\STM32F1xx_DFP\2.4.1\Device\Include -IC:\Keil_v5\ARM\CMSIS\Include --predef
ine="__UVISION_VERSION SETA 514" --predefine="_RTE_ SETA 1" --predefine="STM32F
10X_HD SETA 1" --list=.\listings\startup_stm32f10x_hd.lst RTE\Device\STM32F103Z
E\startup_stm32f10x_hd.s
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
STACK 00000000
Symbol: STACK
Definitions
At line 39 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
None
Comment: STACK unused
Stack_Mem 00000000
Symbol: Stack_Mem
Definitions
At line 40 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 349 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 351 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
__initial_sp 00000400
Symbol: __initial_sp
Definitions
At line 41 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 64 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Comment: __initial_sp used once
3 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
HEAP 00000000
Symbol: HEAP
Definitions
At line 49 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
None
Comment: HEAP unused
Heap_Mem 00000000
Symbol: Heap_Mem
Definitions
At line 51 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 348 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 350 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
__heap_base 00000000
Symbol: __heap_base
Definitions
At line 50 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
None
Comment: __heap_base unused
__heap_limit 00000200
Symbol: __heap_limit
Definitions
At line 52 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
None
Comment: __heap_limit unused
4 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
RESET 00000000
Symbol: RESET
Definitions
At line 59 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
None
Comment: RESET unused
__Vectors 00000000
Symbol: __Vectors
Definitions
At line 64 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 60 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 144 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
__Vectors_End 00000130
Symbol: __Vectors_End
Definitions
At line 142 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 61 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 144 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
3 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.text 00000000
Symbol: .text
Definitions
At line 146 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
None
Comment: .text unused
ADC1_2_IRQHandler 0000001A
Symbol: ADC1_2_IRQHandler
Definitions
At line 284 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 100 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 223 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
ADC3_IRQHandler 0000001A
Symbol: ADC3_IRQHandler
Definitions
At line 313 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 129 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 252 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
BusFault_Handler 0000000E
Symbol: BusFault_Handler
Definitions
At line 176 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 69 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 177 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
CAN1_RX1_IRQHandler 0000001A
Symbol: CAN1_RX1_IRQHandler
Definitions
At line 287 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 103 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 226 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
CAN1_SCE_IRQHandler 0000001A
Symbol: CAN1_SCE_IRQHandler
Definitions
At line 288 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 104 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 227 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
DMA1_Channel1_IRQHandler 0000001A
Symbol: DMA1_Channel1_IRQHandler
Definitions
At line 277 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
ARM Macro Assembler Page 2 Alphabetic symbol ordering
Relocatable symbols
At line 93 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 216 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
DMA1_Channel2_IRQHandler 0000001A
Symbol: DMA1_Channel2_IRQHandler
Definitions
At line 278 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 94 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 217 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
DMA1_Channel3_IRQHandler 0000001A
Symbol: DMA1_Channel3_IRQHandler
Definitions
At line 279 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 95 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 218 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
DMA1_Channel4_IRQHandler 0000001A
Symbol: DMA1_Channel4_IRQHandler
Definitions
At line 280 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 96 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 219 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
DMA1_Channel5_IRQHandler 0000001A
Symbol: DMA1_Channel5_IRQHandler
Definitions
At line 281 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 97 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 220 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
DMA1_Channel6_IRQHandler 0000001A
Symbol: DMA1_Channel6_IRQHandler
Definitions
At line 282 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 98 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 221 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
DMA1_Channel7_IRQHandler 0000001A
Symbol: DMA1_Channel7_IRQHandler
Definitions
At line 283 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 99 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 222 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
DMA2_Channel1_IRQHandler 0000001A
ARM Macro Assembler Page 3 Alphabetic symbol ordering
Relocatable symbols
Symbol: DMA2_Channel1_IRQHandler
Definitions
At line 322 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 138 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 261 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
DMA2_Channel2_IRQHandler 0000001A
Symbol: DMA2_Channel2_IRQHandler
Definitions
At line 323 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 139 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 262 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
DMA2_Channel3_IRQHandler 0000001A
Symbol: DMA2_Channel3_IRQHandler
Definitions
At line 324 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 140 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 263 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
DMA2_Channel4_5_IRQHandler 0000001A
Symbol: DMA2_Channel4_5_IRQHandler
Definitions
At line 325 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 141 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 264 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
DebugMon_Handler 00000014
Symbol: DebugMon_Handler
Definitions
At line 190 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 76 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 191 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Default_Handler 0000001A
Symbol: Default_Handler
Definitions
At line 203 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
None
Comment: Default_Handler unused
EXTI0_IRQHandler 0000001A
Symbol: EXTI0_IRQHandler
Definitions
At line 272 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 88 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 211 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
ARM Macro Assembler Page 4 Alphabetic symbol ordering
Relocatable symbols
EXTI15_10_IRQHandler 0000001A
Symbol: EXTI15_10_IRQHandler
Definitions
At line 306 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 122 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 245 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
EXTI1_IRQHandler 0000001A
Symbol: EXTI1_IRQHandler
Definitions
At line 273 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 89 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 212 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
EXTI2_IRQHandler 0000001A
Symbol: EXTI2_IRQHandler
Definitions
At line 274 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 90 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 213 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
EXTI3_IRQHandler 0000001A
Symbol: EXTI3_IRQHandler
Definitions
At line 275 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 91 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 214 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
EXTI4_IRQHandler 0000001A
Symbol: EXTI4_IRQHandler
Definitions
At line 276 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 92 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 215 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
EXTI9_5_IRQHandler 0000001A
Symbol: EXTI9_5_IRQHandler
Definitions
At line 289 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 105 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 228 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
FLASH_IRQHandler 0000001A
Symbol: FLASH_IRQHandler
Definitions
ARM Macro Assembler Page 5 Alphabetic symbol ordering
Relocatable symbols
At line 270 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 86 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 209 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
FSMC_IRQHandler 0000001A
Symbol: FSMC_IRQHandler
Definitions
At line 314 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 130 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 253 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
HardFault_Handler 0000000A
Symbol: HardFault_Handler
Definitions
At line 166 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 67 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 167 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
I2C1_ER_IRQHandler 0000001A
Symbol: I2C1_ER_IRQHandler
Definitions
At line 298 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 114 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 237 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
I2C1_EV_IRQHandler 0000001A
Symbol: I2C1_EV_IRQHandler
Definitions
At line 297 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 113 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 236 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
I2C2_ER_IRQHandler 0000001A
Symbol: I2C2_ER_IRQHandler
Definitions
At line 300 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 116 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 239 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
I2C2_EV_IRQHandler 0000001A
Symbol: I2C2_EV_IRQHandler
Definitions
At line 299 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 115 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 238 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
ARM Macro Assembler Page 6 Alphabetic symbol ordering
Relocatable symbols
MemManage_Handler 0000000C
Symbol: MemManage_Handler
Definitions
At line 171 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 68 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 172 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
NMI_Handler 00000008
Symbol: NMI_Handler
Definitions
At line 161 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 66 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 162 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
PVD_IRQHandler 0000001A
Symbol: PVD_IRQHandler
Definitions
At line 267 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 83 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 206 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
PendSV_Handler 00000016
Symbol: PendSV_Handler
Definitions
At line 194 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 78 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 195 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
RCC_IRQHandler 0000001A
Symbol: RCC_IRQHandler
Definitions
At line 271 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 87 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 210 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
RTCAlarm_IRQHandler 0000001A
Symbol: RTCAlarm_IRQHandler
Definitions
At line 307 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 123 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 246 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
RTC_IRQHandler 0000001A
Symbol: RTC_IRQHandler
Definitions
At line 269 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
ARM Macro Assembler Page 7 Alphabetic symbol ordering
Relocatable symbols
Uses
At line 85 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 208 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Reset_Handler 00000000
Symbol: Reset_Handler
Definitions
At line 149 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 65 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 150 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
SDIO_IRQHandler 0000001A
Symbol: SDIO_IRQHandler
Definitions
At line 315 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 131 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 254 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
SPI1_IRQHandler 0000001A
Symbol: SPI1_IRQHandler
Definitions
At line 301 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 117 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 240 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
SPI2_IRQHandler 0000001A
Symbol: SPI2_IRQHandler
Definitions
At line 302 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 118 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 241 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
SPI3_IRQHandler 0000001A
Symbol: SPI3_IRQHandler
Definitions
At line 317 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 133 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 256 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
SVC_Handler 00000012
Symbol: SVC_Handler
Definitions
At line 185 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 75 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 186 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
SysTick_Handler 00000018
ARM Macro Assembler Page 8 Alphabetic symbol ordering
Relocatable symbols
Symbol: SysTick_Handler
Definitions
At line 198 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 79 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 199 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
TAMPER_IRQHandler 0000001A
Symbol: TAMPER_IRQHandler
Definitions
At line 268 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 84 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 207 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
TIM1_BRK_IRQHandler 0000001A
Symbol: TIM1_BRK_IRQHandler
Definitions
At line 290 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 106 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 229 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
TIM1_CC_IRQHandler 0000001A
Symbol: TIM1_CC_IRQHandler
Definitions
At line 293 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 109 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 232 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
TIM1_TRG_COM_IRQHandler 0000001A
Symbol: TIM1_TRG_COM_IRQHandler
Definitions
At line 292 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 108 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 231 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
TIM1_UP_IRQHandler 0000001A
Symbol: TIM1_UP_IRQHandler
Definitions
At line 291 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 107 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 230 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
TIM2_IRQHandler 0000001A
Symbol: TIM2_IRQHandler
Definitions
At line 294 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
ARM Macro Assembler Page 9 Alphabetic symbol ordering
Relocatable symbols
At line 110 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 233 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
TIM3_IRQHandler 0000001A
Symbol: TIM3_IRQHandler
Definitions
At line 295 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 111 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 234 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
TIM4_IRQHandler 0000001A
Symbol: TIM4_IRQHandler
Definitions
At line 296 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 112 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 235 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
TIM5_IRQHandler 0000001A
Symbol: TIM5_IRQHandler
Definitions
At line 316 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 132 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 255 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
TIM6_IRQHandler 0000001A
Symbol: TIM6_IRQHandler
Definitions
At line 320 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 136 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 259 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
TIM7_IRQHandler 0000001A
Symbol: TIM7_IRQHandler
Definitions
At line 321 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 137 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 260 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
TIM8_BRK_IRQHandler 0000001A
Symbol: TIM8_BRK_IRQHandler
Definitions
At line 309 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 125 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 248 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
TIM8_CC_IRQHandler 0000001A
ARM Macro Assembler Page 10 Alphabetic symbol ordering
Relocatable symbols
Symbol: TIM8_CC_IRQHandler
Definitions
At line 312 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 128 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 251 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
TIM8_TRG_COM_IRQHandler 0000001A
Symbol: TIM8_TRG_COM_IRQHandler
Definitions
At line 311 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 127 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 250 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
TIM8_UP_IRQHandler 0000001A
Symbol: TIM8_UP_IRQHandler
Definitions
At line 310 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 126 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 249 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
UART4_IRQHandler 0000001A
Symbol: UART4_IRQHandler
Definitions
At line 318 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 134 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 257 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
UART5_IRQHandler 0000001A
Symbol: UART5_IRQHandler
Definitions
At line 319 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 135 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 258 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
USART1_IRQHandler 0000001A
Symbol: USART1_IRQHandler
Definitions
At line 303 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 119 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 242 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
USART2_IRQHandler 0000001A
Symbol: USART2_IRQHandler
Definitions
At line 304 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 120 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
ARM Macro Assembler Page 11 Alphabetic symbol ordering
Relocatable symbols
At line 243 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
USART3_IRQHandler 0000001A
Symbol: USART3_IRQHandler
Definitions
At line 305 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 121 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 244 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
USBWakeUp_IRQHandler 0000001A
Symbol: USBWakeUp_IRQHandler
Definitions
At line 308 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 124 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 247 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
USB_HP_CAN1_TX_IRQHandler 0000001A
Symbol: USB_HP_CAN1_TX_IRQHandler
Definitions
At line 285 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 101 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 224 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
USB_LP_CAN1_RX0_IRQHandler 0000001A
Symbol: USB_LP_CAN1_RX0_IRQHandler
Definitions
At line 286 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 102 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 225 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
UsageFault_Handler 00000010
Symbol: UsageFault_Handler
Definitions
At line 181 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 70 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 182 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
WWDG_IRQHandler 0000001A
Symbol: WWDG_IRQHandler
Definitions
At line 266 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 82 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 205 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
__user_initial_stackheap 0000001C
Symbol: __user_initial_stackheap
ARM Macro Assembler Page 12 Alphabetic symbol ordering
Relocatable symbols
Definitions
At line 346 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 344 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Comment: __user_initial_stackheap used once
73 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Absolute symbols
Heap_Size 00000200
Symbol: Heap_Size
Definitions
At line 47 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 51 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 350 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Stack_Size 00000400
Symbol: Stack_Size
Definitions
At line 37 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 40 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
At line 349 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
__Vectors_Size 00000130
Symbol: __Vectors_Size
Definitions
At line 144 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 62 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Comment: __Vectors_Size used once
3 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
External symbols
SystemInit 00000000
Symbol: SystemInit
Definitions
At line 152 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 153 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Comment: SystemInit used once
__main 00000000
Symbol: __main
Definitions
At line 151 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
At line 155 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Comment: __main used once
__use_two_region_memory 00000000
Symbol: __use_two_region_memory
Definitions
At line 343 in file RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Uses
None
Comment: __use_two_region_memory unused
3 symbols
426 symbols in table
Module/Inc/step_motor.h 0 → 100644
#ifndef STEPPER_MOTOR_H
#define STEPPER_MOTOR_H
#define SYSCLK_FREQUENCY 72000000 // 主时钟频率（72 MHz）
#define STEPMOTOR_ANGLEPERSTEP 1.8 //步进电机步距角
#define STEPMOTOR_FREDIV 32 //步进电机分频系数（细分数）
#define STEPMOTOR_PERDISTANCE 2 //步进电机一转走2mm
#define STEPMOTOR_PULSEPERROUND ((360/STEPMOTOR_ANGLEPERSTEP)*STEPMOTOR_FREDIV) //步进电机每转所需要脉冲的脉冲个数
#define STEPMOTOR_PULSEPERDISTANCE STEPMOTOR_PULSEPERROUND/STEPMOTOR_PERDISTANCE //步进电机每1mm所需要脉冲的脉冲个数
#define STEPMOTOR_FREQ_ROUNDPERMIN (9375/(STEPMOTOR_FREDIV*2)) //步进电机1r/min需要配置的定时器重载值((72000000*60/STEPMOTOR_PULSEPERROUND)/72)（假设时钟分频为8） 定时时间=60s/(每转需要的脉冲个数) 秒冲个数*2是因为只认高-低
#define STEPMOTOR_MAX_SPEED(psc, arr) (SYSCLK_FREQUENCY / ((psc + 1) * (arr + 1)) * 60 / STEPMOTOR_PULSEPERROUND)
typedef enum
{
SPEED_NONE, // 无速度变化
SPEED_ACC, // 加速
SPEED_DEC, // 减速
SPEED_STOP, // 停止
} SpeedStatus;
// 定义步进电机配置结构体
typedef struct {
unsigned stepcount; // 步数（脉冲数）
unsigned direction; // 方向 (0: 逆时针, 1: 顺时针)
unsigned curSpeed; // 当前速度 (步/秒)
unsigned desSpeed; // 目标速度 (步/秒)
unsigned maxSpeed; //最大转速
SpeedStatus speedStatus; // 速度状态
unsigned stepcountMode; // 脉冲计数模式
unsigned curlocation; // 当前位置
unsigned deslocation; // 目标位置
unsigned acceleration; // 加速度 (步/秒^2)
unsigned deceleration; // 减速度 (步/秒^2)
uint16_t psc; //预分频器
uint16_t arr; //自动重装载寄存器
} StepMotor;
// 更新电机状态
void Update_Motor_Status(StepMotor *motor, SpeedStatus status, uint32_t targetSpeed, uint32_t acceleration);
;
void Set_Direction(int direction);
// 使能或禁用步进电机
void Enable_Stepper(bool enable);
// 设置PWM频率
void Set_PWM_Frequency(uint32_t frequency)；
// 梯形加减速算法
void StepMotor(int steps, int direction, int max_speed, int acceleration);
void Delay(uint32_t delay);
void Timer_Frequency(int & frequency,StepMotor *stepMotor);
void TIM3_Init(uint16_t &psc,uint16_t &arr);
#endif // STEPPER_MOTOR_H
\ No newline at end of file
Module/Inc/uart_log.h 0 → 100644
#ifndef UART_LOG_H
#define UART_LOG_H
#include "stm32f10x.h"
// 初始化串口日志
void Serial_Init(void);
// 打印字符串
void Serial_Print(const char *str);
// 打印字符
void Serial_Write(char ch);
// 打印格式化字符串
void Serial_Printf(const char *format, ...);
#endif // UART_LOG_H
Module/Src/step_motor.c 0 → 100644
#include "step_motor.h"
#include "stm32f10x.h"
// 初始化步进电机控制
void StepperMotor_Init(void){
// 使能 GPIOC 和 GPIOF 的时钟
RCC->APB2ENR |= RCC_APB2ENR_IOPCEN;
RCC->APB2ENR |= RCC_APB2ENR_IOPFEN;
// 使能 AFIO 时钟，用于重映射
RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;
// 配置 PC6 引脚为复用推挽输出 (50 MHz)
GPIOC->CRL &= ~(0xF << 24); // 清空 PC6 配置
GPIOC->CRL |= (0xB << 24); // 配置为复用推挽输出 (0xB = 1011)
// 配置 PC5 为通用推挽输出 (方向)
GPIOC->CRL &= ~(0xF << 20); // 清空 PC5 配置
GPIOC->CRL |= (0x3 << 20); // 配置为通用推挽输出 (0x3 = 0011)
// 配置 PF11 为通用推挽输出 (使能)
GPIOF->CRH &= ~(0xF <<12); // 清空 PF11 配置
GPIOF->CRH |= (0x3 << 12); // 配置为通用推挽输出 (0x3 = 0011)
// 重映射 TIM3_CH1 到 PC6
AFIO->MAPR |= AFIO_MAPR_TIM3_REMAP_FULLREMAP;
}
// 初始化定时器 TIM3 函数
void TIM3_Init(uint16_t &psc,uint16_t &arr);
// 使能 TIM3 时钟
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
// 设置预分频器为 72-1，使时钟频率为 1 MHz (72 MHz / 72)
TIM3->PSC = psc;//72 - 1;
// 设置自动重装载值为 1000 - 1，对应于 1 毫秒 (1 MHz * 1 ms)
TIM3->ARR =arr;//1000 - 1;
// 配置 TIM3 通道 1 为 PWM 模式 1
TIM3->CCMR1 &= ~TIM_CCMR1_OC1M; // 清空模式位
TIM3->CCMR1 |= TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; // PWM 模式1
TIM3->CCER |= TIM_CCER_CC1E; // 使能通道 1 输出
TIM3->CCR1 = 500; // 设置占空比为 50%
// 使能 TIM3
TIM3->CR1 |= TIM_CR1_CEN;
}
//f定时器输出频率 系统时钟/(PSC+1)*(ARR+1)
void Timer_Frequency(int &frequency, StepMotor *stepMotor) {
// 预先计算 psc 和 arr
int psc_plus_1 = stepMotor->psc + 1;
int arr_plus_1 = stepMotor->arr + 1;
// 简化并避免除法的额外开销
frequency = 72000000 / (psc_plus_1 * arr_plus_1);
}
// 设置方向
// 设置方向函数
void Set_Direction(int direction) {
if (direction) {
GPIOC->ODR |= (1 << 5); // 设置高电平 (顺时针方向)
} else {
GPIOC->ODR &= ~(1 << 5); // 设置低电平 (逆时针方向)
}
}
// 使能控制函数
void Enable_Stepper(bool enable) {
if (enable) {
GPIOF->ODR &= ~(1 << 11); // 设置低电平 (使能步进电机)
} else {
GPIOF->ODR |= (1 << 11); // 设置高电平 (关闭步进电机)
}
}
// 设置PWM频率
void Set_PWM_Frequency(uint32_t frequency) {
// 计算ARR值
uint32_t arr_value = (SYSCLK_FREQUENCY / ((TIM3->PSC + 1) * frequency)) - 1;
// 更新自动重装载寄存器
TIM3->ARR = arr_value;
TIM3->CCR1 = arr_value / 2; // 保持50%占空比
}
// 梯形加速函数
void StepMotor_Accelerate(uint32_t targetRPM, uint32_t acceleration) {
uint32_t currentRPM = 0;
uint32_t deltaRPM = (acceleration / 60000) * 10; // 10ms内的速度增量
while (currentRPM < targetRPM) {
if (currentRPM == 0) {
currentRPM = 100;
}
// 更新PWM频率
uint32_t pwmFrequency = (currentRPM * STEPMOTOR_PULSEPERROUND) / 60;
Set_PWM_Frequency(pwmFrequency);
// 每次加速的增量
currentRPM += deltaRPM;
if (currentRPM > targetRPM) {
currentRPM = targetRPM; // 防止超过目标速度
}
// 延时 10ms，每次迭代增加速度
Delay(10);
}
// 达到目标速度，保持目标速度的PWM频率
uint32_t finalFrequency = (targetRPM * STEPMOTOR_PULSEPERROUND) / 60;
Set_PWM_Frequency(finalFrequency);
}
// 梯形减速函数：将当前转速逐步减速为 0
void StepMotor_Decelerate(uint32_t currentRPM, uint32_t deceleration) {
uint32_t deltaRPM = (deceleration / 60000) * 10; // 10ms 内的速度减量
while (currentRPM > 0) {
// 计算 PWM 频率
uint32_t pwmFrequency = (currentRPM * STEPMOTOR_PULSEPERROUND) / 60;
Set_PWM_Frequency(pwmFrequency); // 更新PWM频率以调整电机速度
// 每次减速的增量
if (currentRPM > deltaRPM) {
currentRPM -= deltaRPM; // 减速
} else {
currentRPM = 0;
}
Delay(10);
}
Set_PWM_Frequency(0);
}
void Delay(uint32_t delay) {
for (volatile uint32_t i = 0; i < delay * 1000; i++) {
__NOP(); // 空操作，用于延时
}
}
void Update_Motor_Status(StepMotor *motor, SpeedStatus status, uint32_t targetSpeed, uint32_t acceleration) {
motor->speedStatus = status; // 更新电机的速度状态
motor->desSpeed = targetSpeed; // 更新目标速度
motor->acceleration = acceleration; // 更新加速度
switch (status) {
case SPEED_ACC:
// 加速过程
StepMotor_Accelerate(targetSpeed, acceleration);
break;
case SPEED_DEC:
// 减速过程
StepMotor_Decelerate(motor->curSpeed, acceleration);
break;
case SPEED_NONE:
// 匀速，保持当前速度
Set_PWM_Frequency((motor->curSpeed * STEPMOTOR_PULSEPERROUND) / 60);
break;
case SPEED_STOP:
// 停止电机
motor->curSpeed = 0;
Set_PWM_Frequency(0); // 关闭PWM
break;
default:
break;
}
}
Module/Src/uart_log.c 0 → 100644
#include "uart_log.h"
#include <stdarg.h>
#include <string.h>
#include <stdio.h> // 包含<stdio.h>头文件
// 缓冲区大小
#define SERIAL_BUFFER_SIZE 128
// USART1 GPIO初始化
void USART1_GPIO_Init(void) {
// 使能GPIOA和USART1时钟
RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_USART1EN;
GPIOA->CRH &= ~(0xF << 20);
GPIOA->CRH |= (0xB << 20);
GPIOA->CRH &= ~(0xF << 24); // 清除模式控制位
GPIOA->CRH |= (0x4 << 24); // 设置为浮空输入
}
// USART1初始化
void USART1_Init(void) {
// 设置波特率
uint32_t BRR = (uint32_t)(SystemCoreClock / 16 / 115200);
USART1->BRR = BRR;
// 配置USART1
USART1->CR1 = USART_CR1_UE | USART_CR1_TE | USART_CR1_RE; // 使能USART1、发送器和接收器
USART1->CR2 = 0; // 不使用流控制
USART1->CR3 = 0; // 不使用额外功能
}
// 发送一个字符
void USART1_SendChar(char ch) {
while (!(USART1->SR & USART_SR_TXE)); // 等待发送缓冲区为空
USART1->DR = (ch & 0xFF); // 发送字符
}
// 发送字符串
void USART1_SendString(const char *str) {
while (*str) {
USART1_SendChar(*str++);
}
}
// 格式化字符串并发送
void USART1_SendFormatted(const char *format, ...) {
char buffer[SERIAL_BUFFER_SIZE];
va_list args;
va_start(args, format);
vsnprintf(buffer, sizeof(buffer), format, args);
va_end(args);
USART1_SendString(buffer);
}
// 初始化串口日志
void Serial_Init(void) {
USART1_GPIO_Init();
USART1_Init();
}
// 打印字符串
void Serial_Print(const char *str) {
USART1_SendString(str);
}
// 打印字符
void Serial_Write(char ch) {
USART1_SendChar(ch);
}
// 打印格式化字符串
void Serial_Printf(const char *format, ...) {
va_list args;
va_start(args, format);
USART1_SendFormatted(format, args);
va_end(args);
}
MotorControl.uvguix.14347 0 → 100644
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectGui xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_guix.xsd">
<SchemaVersion>-5.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<ViewPool/>
<SECTreeCtrl>
<View>
<WinId>38003</WinId>
<ViewName>Registers</ViewName>
<TableColWidths>115 275</TableColWidths>
</View>
<View>
<WinId>346</WinId>
<ViewName>Code Coverage</ViewName>
<TableColWidths>370 160</TableColWidths>
</View>
<View>
<WinId>204</WinId>
<ViewName>Performance Analyzer</ViewName>
<TableColWidths>530</TableColWidths>
</View>
</SECTreeCtrl>
<TreeListPane>
<View>
<WinId>1506</WinId>
<ViewName>Symbols</ViewName>
<UserString></UserString>
<TableColWidths>133 133 133</TableColWidths>
</View>
<View>
<WinId>1936</WinId>
<ViewName>Watch 1</ViewName>
<UserString></UserString>
<TableColWidths>133 133 133</TableColWidths>
</View>
<View>
<WinId>1937</WinId>
<ViewName>Watch 2</ViewName>
<UserString></UserString>
<TableColWidths>133 133 133</TableColWidths>
</View>
<View>
<WinId>1935</WinId>
<ViewName>Call Stack + Locals</ViewName>
<UserString></UserString>
<TableColWidths>133 133 133</TableColWidths>
</View>
<View>
<WinId>2506</WinId>
<ViewName>Trace Data</ViewName>
<UserString></UserString>
<TableColWidths>75 135 130 95 70 230 200 150</TableColWidths>
</View>
</TreeListPane>
<WindowSettings>
<LogicAnalizer>
<ShowLACursor>1</ShowLACursor>
<ShowSignalInfo>1</ShowSignalInfo>
<ShowCycles>0</ShowCycles>
<LeftSideBarSize>0</LeftSideBarSize>
<TimeBaseIndex>-1</TimeBaseIndex>
</LogicAnalizer>
</WindowSettings>
<WinLayoutEx>
<sActiveDebugView></sActiveDebugView>
<WindowPosition>
<length>44</length>
<flags>2</flags>
<showCmd>3</showCmd>
<MinPosition>
<xPos>-1</xPos>
<yPos>-1</yPos>
</MinPosition>
<MaxPosition>
<xPos>-1</xPos>
<yPos>-1</yPos>
</MaxPosition>
<NormalPosition>
<Top>79</Top>
<Left>159</Left>
<Right>1119</Right>
<Bottom>600</Bottom>
</NormalPosition>
</WindowPosition>
<MDIClientArea>
<RegID>0</RegID>
<MDITabState>
<Len>1001</Len>
<Data>0100000004000000010000000100000001000000010000000000000002000000000000000100000001000000000000002800000028000000010000000A00000004000000010000002A433A5C4B65696C5F76355C41524D5C434D5349535C496E636C7564655C636D7369735F61726D63632E68000000000D636D7369735F61726D63632E6800000000B3A6BE00FFFFFFFF31443A5CC7B6C8EBCABD5C6D63755C4D6F746F725F436F6E74726F6C5C4D6F64756C655C5372635C756172745F6C6F672E63000000000A756172745F6C6F672E6300000000C5D4F200FFFFFFFF32443A5CC7B6C8EBCABD5C6D63755C4D6F746F725F436F6E74726F6C5C4D6F64756C655C5372635C537465704D6F746F722E63000000000B537465704D6F746F722E6300000000A5C2D700FFFFFFFF31443A5CC7B6C8EBCABD5C6D63755C4D6F746F725F436F6E74726F6C5C4D6F64756C655C496E635C756172745F6C6F672E68000000000A756172745F6C6F672E6800000000D9ADC200FFFFFFFF32443A5CC7B6C8EBCABD5C6D63755C4D6F746F725F436F6E74726F6C5C4D6F64756C655C496E635C537465704D6F746F722E68000000000B537465704D6F746F722E6800000000F7B88600FFFFFFFF22443A5CC7B6C8EBCABD5C6D63755C4D6F746F725F436F6E74726F6C5C6D61696E2E6300000000066D61696E2E63000000009CC1B600FFFFFFFF35443A5CC7B6C8EBCABD5C6D63755C4D6F746F725F436F6E74726F6C5C4C697374696E67735C4D6F746F72436F6E74726F6C2E6D617000000000104D6F746F72436F6E74726F6C2E6D617000000000BCA8E100FFFFFFFF49443A5CC7B6C8EBCABD5C6D63755C4D6F746F725F436F6E74726F6C5C5254455C4465766963655C53544D3332463130335A455C737461727475705F73746D3332663130785F68642E730000000016737461727475705F73746D3332663130785F68642E7300000000F0A0A100FFFFFFFF34443A5CC7B6C8EBCABD5C6D63755C4D6F746F725F436F6E74726F6C5C4F626A656374735C4D6F746F72436F6E74726F6C2E73637400000000104D6F746F72436F6E74726F6C2E73637400000000BECEA100FFFFFFFF47433A5C4B65696C5F76355C41524D5C5061636B5C4B65696C5C53544D3332463178785F4446505C322E322E305C4465766963655C496E636C7564655C73746D3332663130782E68000000000B73746D3332663130782E6800000000FFDC7800FFFFFFFF0100000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD5000100000000000000020000009401000066000000000500003D020000</Data>
</MDITabState>
</MDIClientArea>
<ViewEx>
<ViewType>0</ViewType>
<ViewName>Build</ViewName>
<Window>
<RegID>-1</RegID>
<PaneID>-1</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>940100004F000000B0030000B3000000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>9401000066000000B0030000CA000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>1005</RegID>
<PaneID>1005</PaneID>
<IsVisible>1</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>00000000630000009001000026020000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>109</RegID>
<PaneID>109</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>03000000660000008D0100000D020000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000DE000000C6010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>1465</RegID>
<PaneID>1465</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>030000007D010000AD030000C4010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>1466</RegID>
<PaneID>1466</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>030000007D010000AD030000C4010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>1467</RegID>
<PaneID>1467</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>030000007D010000AD030000C4010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>1468</RegID>
<PaneID>1468</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>030000007D010000AD030000C4010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>1506</RegID>
<PaneID>1506</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>16384</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>1913</RegID>
<PaneID>1913</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>9701000066000000AD0300009A000000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>1935</RegID>
<PaneID>1935</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>030000007D010000AD030000C4010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>1936</RegID>
<PaneID>1936</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>030000007D010000AD030000C4010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>1937</RegID>
<PaneID>1937</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>030000007D010000AD030000C4010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>1939</RegID>
<PaneID>1939</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>030000007D010000AD030000C4010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>1940</RegID>
<PaneID>1940</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>030000007D010000AD030000C4010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>1941</RegID>
<PaneID>1941</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>030000007D010000AD030000C4010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>1942</RegID>
<PaneID>1942</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>030000007D010000AD030000C4010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>195</RegID>
<PaneID>195</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>1</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>03000000660000008D0100004E010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000DE000000C6010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>196</RegID>
<PaneID>196</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>03000000660000008D0100000D020000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000DE000000C6010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>197</RegID>
<PaneID>197</PaneID>
<IsVisible>1</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>000000003E02000000050000C6020000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>198</RegID>
<PaneID>198</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>0000000066010000B0030000DD010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>199</RegID>
<PaneID>199</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>0300000041020000FD040000AD020000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>203</RegID>
<PaneID>203</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>8192</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>9701000066000000AD0300009A000000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>204</RegID>
<PaneID>204</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>9701000066000000AD0300009A000000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>221</RegID>
<PaneID>221</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>00000000000000000000000000000000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>0A0000000A0000006E0000006E000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>2506</RegID>
<PaneID>2506</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>2507</RegID>
<PaneID>2507</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>030000007D010000AD030000C4010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>343</RegID>
<PaneID>343</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>9701000066000000AD0300009A000000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>346</RegID>
<PaneID>346</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>9701000066000000AD0300009A000000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35824</RegID>
<PaneID>35824</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>9701000066000000AD0300009A000000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35885</RegID>
<PaneID>35885</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35886</RegID>
<PaneID>35886</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35887</RegID>
<PaneID>35887</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35888</RegID>
<PaneID>35888</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35889</RegID>
<PaneID>35889</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35890</RegID>
<PaneID>35890</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35891</RegID>
<PaneID>35891</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35892</RegID>
<PaneID>35892</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35893</RegID>
<PaneID>35893</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35894</RegID>
<PaneID>35894</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35895</RegID>
<PaneID>35895</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35896</RegID>
<PaneID>35896</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35897</RegID>
<PaneID>35897</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35898</RegID>
<PaneID>35898</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35899</RegID>
<PaneID>35899</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35900</RegID>
<PaneID>35900</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35901</RegID>
<PaneID>35901</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35902</RegID>
<PaneID>35902</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35903</RegID>
<PaneID>35903</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35904</RegID>
<PaneID>35904</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>35905</RegID>
<PaneID>35905</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>2302000066000000AD0300005C010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>38003</RegID>
<PaneID>38003</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>03000000660000008D0100000D020000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000DE000000C6010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>38007</RegID>
<PaneID>38007</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>0300000041020000FD040000AD020000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000FA0100009C000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>436</RegID>
<PaneID>436</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>0300000041020000FD040000AD020000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000DE000000C6010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>437</RegID>
<PaneID>437</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>030000007D010000AD030000C4010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>440</RegID>
<PaneID>440</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>030000007D010000AD030000C4010000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>2200000039000000B2010000C9010000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>59392</RegID>
<PaneID>59392</PaneID>
<IsVisible>1</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>940</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>8192</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>0000000000000000B70300001C000000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>0A0000000A0000006E0000006E000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>59393</RegID>
<PaneID>0</PaneID>
<IsVisible>1</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>00000000C602000000050000D9020000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>0A0000000A0000006E0000006E000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>59399</RegID>
<PaneID>59399</PaneID>
<IsVisible>1</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>463</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>8192</RecentFrameAlignment>
<RecentRowIndex>1</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>000000001C000000DA01000038000000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>0A0000000A0000006E0000006E000000</Data>
</RectRecentFloat>
</Window>
<Window>
<RegID>59400</RegID>
<PaneID>59400</PaneID>
<IsVisible>0</IsVisible>
<IsFloating>0</IsFloating>
<IsTabbed>0</IsTabbed>
<IsActivated>0</IsActivated>
<MRUWidth>612</MRUWidth>
<PinState>0</PinState>
<RecentFrameAlignment>8192</RecentFrameAlignment>
<RecentRowIndex>2</RecentRowIndex>
<RectRecentDocked>
<Len>16</Len>
<Data>00000000380000006F02000054000000</Data>
</RectRecentDocked>
<RectRecentFloat>
<Len>16</Len>
<Data>0A0000000A0000006E0000006E000000</Data>
</RectRecentFloat>
</Window>
<DockMan>
<Len>2675</Len>
<Data>000000000B000000000000000020000000000000FFFFFFFFFFFFFFFF94010000B3000000B0030000B7000000000000000100000004000000010000000000000000000000FFFFFFFF06000000CB00000057010000CC000000F08B00005A01000079070000FFFF02000B004354616262656450616E6500200000000000009401000066000000B0030000CA000000940100004F000000B0030000B30000000000000040280046060000000B446973617373656D626C7900000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657200000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000000000000FFFFFFFFFFFFFFFF1C0200004F0000002002000075010000000000000200000004000000010000000000000000000000FFFFFFFF17000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C0000018000400000000000002002000066000000B00300008C010000200200004F000000B0030000750100000000000040410046170000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF00000000003D8C000001000000FFFFFFFFFFFFFFFF00000000003E8C000001000000FFFFFFFFFFFFFFFF00000000003F8C000001000000FFFFFFFFFFFFFFFF0000000000408C000001000000FFFFFFFFFFFFFFFF0000000000418C000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFF900100004F0000009401000026020000010000000200001004000000010000000000000000000000FFFFFFFF04000000ED0300006D00000073940000C4000000018000100000010000000000000066000000900100003D020000000000004F00000090010000260200000000000040410056040000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73000000006D00000001000000FFFFFFFFFFFFFFFF09526567697374657273000000007394000001000000FFFFFFFFFFFFFFFF0954656D706C6174657300000000C400000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000000000000FFFFFFFFFFFFFFFF0000000062010000B00300006601000000000000010000000400000001000000000000000000000000000000000000000000000001000000C6000000FFFFFFFF0E0000008F070000930700009407000095070000960700009007000091070000B5010000B8010000B9050000BA050000BB050000BC050000CB09000001800080000000000000000000007D010000B0030000F40100000000000066010000B0030000DD01000000000000404100460E0000001343616C6C20537461636B202B204C6F63616C73000000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031000000009007000001000000FFFFFFFFFFFFFFFF0757617463682032000000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF084D656D6F7279203100000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFFFFFFFFFF0000000001000000000000000000000001000000FFFFFFFFD801000066010000DC010000DD01000000000000020000000400000000000000000000000000000000000000000000000000000002000000C6000000FFFFFFFF8F07000001000000FFFFFFFF8F07000001000000C6000000000000000080000001000000FFFFFFFFFFFFFFFF0000000026020000000500002A0200000100000001000010040000000100000000FFFFFF6C010000FFFFFFFF04000000C7000000B401000077940000C500000001800080000001000000000000004102000000050000DD020000000000002A02000000050000C60200000000000040820056040000000D46696E6420496E2046696C657300000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0742726F77736572000000007794000001000000FFFFFFFFFFFFFFFF0C4275696C64204F757470757401000000C500000001000000FFFFFFFFFFFFFFFF03000000000000000000000000000000000000000000000001000000FFFFFFFFC700000001000000FFFFFFFFC700000001000000FFFF02001400434D756C746950616E654672616D65576E644578000100842200000039000000DE000000C601000000000000000000000200000000000000C30000000000000000000000000000000000000001000000C30000000000000000000000</Data>
</DockMan>
<ToolBar>
<RegID>59392</RegID>
<Name>File</Name>
<Buttons>
<Len>2055</Len>
<Data>00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000004000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000004000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE803000000000000000000000000000000000000000000000001000000010000009600000002002050000000000E456E61626C655F53746570706572960000000000000002000E456E61626C655F537465707065720F54494D325F49525148616E646C65720000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000020000001500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000000180C8880000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E4C010000020001001A0000000F50726F6A6563742057696E646F7773000000000000000000000000010000000100000000000000000000000100000008002880DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002880DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002880E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002880E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000288018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000028800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002880D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002880E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65AC030000</Data>
</Buttons>
<OriginalItems>
<Len>1423</Len>
<Data>2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000</Data>
</OriginalItems>
<OrigResetItems>
<Len>1423</Len>
<Data>2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000</Data>
</OrigResetItems>
</ToolBar>
<ToolBar>
<RegID>59399</RegID>
<Name>Build</Name>
<Buttons>
<Len>668</Len>
<Data>00200000010000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000004001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E00000000000000000000000000000000010000000100000001809E8A0000000000001F0000000000000000000000000000000001000000010000000180D17F0000000004002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA00000000000000000000000000000000000000000000000001000000010000009600000003002050000000000350574D960000000000000001000350574D000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000400240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64CF010000</Data>
</Buttons>
<OriginalItems>
<Len>583</Len>
<Data>1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000</Data>
</OriginalItems>
<OrigResetItems>
<Len>583</Len>
<Data>1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000</Data>
</OrigResetItems>
</ToolBar>
<ToolBar>
<RegID>59400</RegID>
<Name>Debug</Name>
<Buttons>
<Len>2220</Len>
<Data>00200000000000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000000002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000000000002D0000000000000000000000000000000001000000010000000180F07F0000000000002E0000000000000000000000000000000001000000010000000180E8880000000000003700000000000000000000000000000000010000000100000001803B010000000000002F0000000000000000000000000000000001000000010000000180BB8A00000000000030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000000000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000002001380D88B000000000000310000000757617463682031000000000000000000000000010000000100000000000000000000000100000000001380D98B0000000000003100000007576174636820320000000000000000000000000100000001000000000000000000000001000000000013800F01000000000000320000000E4D656D6F72792057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000084D656D6F72792031000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000084D656D6F72792032000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000084D656D6F72792033000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000084D656D6F727920340000000000000000000000000100000001000000000000000000000001000000000013801001000000000000330000000E53657269616C2057696E646F77730000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000755415254202331000000000000000000000000010000000100000000000000000000000100000000001380940700000000000033000000075541525420233200000000000000000000000001000000010000000000000000000000010000000000138095070000000000003300000007554152542023330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000000E49544D2F525441205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000003400000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380658A000000000000340000000E4C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E00000014506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000D436F646520436F76657261676500000000000000000000000001000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720000000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720000000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000138001890000000000003600000007546F6F6C626F7800000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730000000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72000000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000</Data>
</Buttons>
<OriginalItems>
<Len>898</Len>
<Data>1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000</Data>
</OriginalItems>
<OrigResetItems>
<Len>898</Len>
<Data>1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000</Data>
</OrigResetItems>
</ToolBar>
<ControlBarsSummary>
<Bars>0</Bars>
<ScreenCX>1280</ScreenCX>
<ScreenCY>800</ScreenCY>
</ControlBarsSummary>
</ViewEx>
</WinLayoutEx>
<MDIGroups>
<Orientation>1</Orientation>
<ActiveMDIGroup>0</ActiveMDIGroup>
<MDIGroup>
<Size>100</Size>
<ActiveTab>4</ActiveTab>
<Doc>
<Name>C:\Keil_v5\ARM\CMSIS\Include\cmsis_armcc.h</Name>
<ColumnNumber>0</ColumnNumber>
<TopLine>1</TopLine>
<CurrentLine>1</CurrentLine>
<Folding>1</Folding>
<ContractedFolders></ContractedFolders>
<PaneID>0</PaneID>
</Doc>
<Doc>
<Name>.\Module\Src\uart_log.c</Name>
<ColumnNumber>4</ColumnNumber>
<TopLine>42</TopLine>
<CurrentLine>66</CurrentLine>
<Folding>1</Folding>
<ContractedFolders></ContractedFolders>
<PaneID>0</PaneID>
</Doc>
<Doc>
<Name>.\Module\Src\StepMotor.c</Name>
<ColumnNumber>0</ColumnNumber>
<TopLine>1</TopLine>
<CurrentLine>1</CurrentLine>
<Folding>1</Folding>
<ContractedFolders></ContractedFolders>
<PaneID>0</PaneID>
</Doc>
<Doc>
<Name>.\Module\Inc\uart_log.h</Name>
<ColumnNumber>0</ColumnNumber>
<TopLine>1</TopLine>
<CurrentLine>1</CurrentLine>
<Folding>1</Folding>
<ContractedFolders></ContractedFolders>
<PaneID>0</PaneID>
</Doc>
<Doc>
<Name>.\Module\Inc\StepMotor.h</Name>
<ColumnNumber>0</ColumnNumber>
<TopLine>1</TopLine>
<CurrentLine>1</CurrentLine>
<Folding>1</Folding>
<ContractedFolders></ContractedFolders>
<PaneID>0</PaneID>
</Doc>
<Doc>
<Name>.\main.c</Name>
<ColumnNumber>17</ColumnNumber>
<TopLine>1</TopLine>
<CurrentLine>1</CurrentLine>
<Folding>1</Folding>
<ContractedFolders></ContractedFolders>
<PaneID>0</PaneID>
</Doc>
<Doc>
<Name>D:\嵌入式\mcu\Motor_Control\Listings\MotorControl.map</Name>
<ColumnNumber>0</ColumnNumber>
<TopLine>1</TopLine>
<CurrentLine>1</CurrentLine>
<Folding>1</Folding>
<ContractedFolders></ContractedFolders>
<PaneID>0</PaneID>
</Doc>
<Doc>
<Name>RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s</Name>
<ColumnNumber>0</ColumnNumber>
<TopLine>1</TopLine>
<CurrentLine>1</CurrentLine>
<Folding>1</Folding>
<ContractedFolders></ContractedFolders>
<PaneID>0</PaneID>
</Doc>
<Doc>
<Name>D:\嵌入式\mcu\Motor_Control\Objects\MotorControl.sct</Name>
<ColumnNumber>0</ColumnNumber>
<TopLine>1</TopLine>
<CurrentLine>7</CurrentLine>
<Folding>1</Folding>
<ContractedFolders></ContractedFolders>
<PaneID>0</PaneID>
</Doc>
<Doc>
<Name>C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h</Name>
<ColumnNumber>19</ColumnNumber>
<TopLine>1003</TopLine>
<CurrentLine>1008</CurrentLine>
<Folding>1</Folding>
<ContractedFolders></ContractedFolders>
<PaneID>0</PaneID>
</Doc>
</MDIGroup>
</MDIGroups>
</ProjectGui>
MotorControl.uvoptx 0 → 100644
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>PWM</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>18</CpuCode>
<Books>
<Book>
<Number>0</Number>
<Title>Quick Start Guide (MCBSTM32E)</Title>
<Path>C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1\Boards/Keil/MCBSTM32E/Documentation/STM32E_QSG.pdf</Path>
</Book>
<Book>
<Number>1</Number>
<Title>Base Board Schematics (MCBSTM32E)</Title>
<Path>C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1\Boards/Keil/MCBSTM32E/Documentation/mcbstm32e-base-board-schematics.pdf</Path>
</Book>
<Book>
<Number>2</Number>
<Title>Display Board Schematics (MCBSTM32E)</Title>
<Path>C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1\Boards/Keil/MCBSTM32E/Documentation/mcbstm32e-display-board-schematics.pdf</Path>
</Book>
<Book>
<Number>3</Number>
<Title>User Manual (MCBSTM32E)</Title>
<Path>C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1\Boards/Keil/MCBSTM32E/Documentation/mcbstm32e.chm</Path>
</Book>
<Book>
<Number>4</Number>
<Title>MCBSTM32E Evaluation Board Web Page (MCBSTM32E)</Title>
<Path>http://www.keil.com/mcbstm32e/</Path>
</Book>
</Books>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<nTsel>1</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\UL2CM3.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:STM32F103ZE$Flash/STM32F10x_512.FLM))</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<DebugDescription>
<Enable>1</Enable>
<EnableLog>0</EnableLog>
<Protocol>2</Protocol>
<DbgClock>10000000</DbgClock>
</DebugDescription>
</TargetOption>
</Target>
<Group>
<GroupName>Control</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Module</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Module\Inc\StepMotor.h</PathWithFileName>
<FilenameWithoutPath>StepMotor.h</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Module\Inc\uart_log.h</PathWithFileName>
<FilenameWithoutPath>uart_log.h</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Module\Src\StepMotor.c</PathWithFileName>
<FilenameWithoutPath>StepMotor.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\Module\Src\uart_log.c</PathWithFileName>
<FilenameWithoutPath>uart_log.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>::Device</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>
MotorControl.uvprojx 0 → 100644
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>PWM</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<TargetCommonOption>
<Device>STM32F103ZE</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32F1xx_DFP.2.4.1</PackID>
<PackURL>https://www.keil.com/pack/</PackURL>
<Cpu>IROM(0x08000000,0x00080000) IRAM(0x20000000,0x00010000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:STM32F103ZE$Flash/STM32F10x_512.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:STM32F103ZE$Device/Include/stm32f10x.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:STM32F103ZE$SVD/STM32F103xx.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>MotorControl</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -REMAP</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
<RestoreSysVw>1</RestoreSysVw>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<RestoreTracepoints>1</RestoreTracepoints>
<RestoreSysVw>1</RestoreSysVw>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>1</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
<Driver>BIN\UL2CM3.DLL</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M3"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x10000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x80000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x80000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x10000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<useXO>0</useXO>
<VariousControls>
<MiscControls>--locale=english --c99</MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include;C:\Keil_v5\ARM\CMSIS\Include;.\Module\Inc</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x08000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc>-u _printf</Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Control</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>.\main.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Module</GroupName>
<Files>
<File>
<FileName>StepMotor.h</FileName>
<FileType>5</FileType>
<FilePath>.\Module\Inc\StepMotor.h</FilePath>
</File>
<File>
<FileName>uart_log.h</FileName>
<FileType>5</FileType>
<FilePath>.\Module\Inc\uart_log.h</FilePath>
</File>
<File>
<FileName>StepMotor.c</FileName>
<FileType>1</FileType>
<FilePath>.\Module\Src\StepMotor.c</FilePath>
</File>
<File>
<FileName>uart_log.c</FileName>
<FileType>1</FileType>
<FilePath>.\Module\Src\uart_log.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::Device</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components>
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32F1xx CMSIS">
<package name="STM32F1xx_DFP" schemaVersion="1.7.2" url="https://www.keil.com/pack/" vendor="Keil" version="2.4.1"/>
<targetInfos>
<targetInfo name="PWM"/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="header" name="RTE_Driver\Config\RTE_Device.h" version="1.1.2">
<instance index="0">RTE\Device\STM32F103ZE\RTE_Device.h</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32F1xx CMSIS"/>
<package name="STM32F1xx_DFP" schemaVersion="1.7.2" url="https://www.keil.com/pack/" vendor="Keil" version="2.4.1"/>
<targetInfos>
<targetInfo name="PWM"/>
</targetInfos>
</file>
<file attr="config" category="source" condition="STM32F1xx HD ARMCC" name="Device\Source\ARM\startup_stm32f10x_hd.s" version="1.0.1">
<instance index="0">RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32F1xx CMSIS"/>
<package name="STM32F1xx_DFP" schemaVersion="1.7.2" url="https://www.keil.com/pack/" vendor="Keil" version="2.4.1"/>
<targetInfos>
<targetInfo name="PWM"/>
</targetInfos>
</file>
<file attr="config" category="source" name="Device\Source\system_stm32f10x.c" version="1.0.1">
<instance index="0">RTE\Device\STM32F103ZE\system_stm32f10x.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="STM32F1xx CMSIS"/>
<package name="STM32F1xx_DFP" schemaVersion="1.7.2" url="https://www.keil.com/pack/" vendor="Keil" version="2.4.1"/>
<targetInfos>
<targetInfo name="PWM"/>
</targetInfos>
</file>
</files>
</RTE>
</Project>
Objects/MotorControl.build_log.htm 0 → 100644
<html>
<body>
<pre>
<h1>Vision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: Vision V5.14.0.0
Copyright (C) 2015 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: 111 1434736858@qq.com, 111, LIC=14HV2-915PI-BSHYX-HP4J5-5IIFN-ZG5AK
Tool Versions:
Toolchain: MDK-ARM Standard Version: 5.14.0.0
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.05 update 1 (build 106)
Assembler: Armasm.exe V5.05 update 1 (build 106)
Linker/Locator: ArmLink.exe V5.05 update 1 (build 106)
Library Manager: ArmAr.exe V5.05 update 1 (build 106)
Hex Converter: FromElf.exe V5.05 update 1 (build 106)
CPU DLL: SARMCM3.DLL V5.14.0.0
Dialog DLL: DCM.DLL V1.13.1.0
Target DLL: UL2CM3.DLL V1.155.0.0
Dialog DLL: TCM.DLL V1.14.4.0
<h2>Project:</h2>
D:\Ƕʽ\mcu\Motor_Control\MotorControl.uvprojx
Project File Date: 09/25/2024
<h2>Output:</h2>
Build target 'PWM'
compiling main.c...
compiling uart_log.c...
compiling step_motor.c...
assembling startup_stm32f10x_hd.s...
compiling system_stm32f10x.c...
linking...
Program Size: Code=1196 RO-data=336 RW-data=20 ZI-data=1636
FromELF: creating hex file...
".\Objects\MotorControl.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: Keil
https://www.keil.com/pack/Keil.STM32F1xx_DFP.2.4.1.pack
Keil::Device:Startup:1.0.0
STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
* Component: Startup Version: 1.0.0
<h2>Collection of Component include folders:</h2>
D:\Ƕʽ\mcu\Motor_Control\RTE
D:\Ƕʽ\mcu\Motor_Control\RTE\Device\STM32F103ZE
C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1
C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1\Device\Include
<h2>Collection of Component Files used:</h2>
* Component: Keil::Device:Startup:1.0.0
Source file: Device\Source\ARM\startup_stm32f10x_hd.s
Source file: Device\Source\ARM\STM32F1xx_OPT.s
Source file: Device\Source\system_stm32f10x.c
Include file: RTE_Driver\Config\RTE_Device.h
</pre>
</body>
</html>
Objects/MotorControl.hex 0 → 100644
:020000040800F2
:1000000078060020CD010008D5010008D7010008BE
:10001000D9010008DB010008DD0100080000000034
:10002000000000000000000000000000DF010008E8
:10003000E101000800000000E3010008E5010008FC
:10004000E7010008E7010008E7010008E7010008F0
:10005000E7010008E7010008E7010008E7010008E0
:10006000E7010008E7010008E7010008E7010008D0
:10007000E7010008E7010008E7010008E7010008C0
:10008000E7010008E7010008E7010008E7010008B0
:10009000E7010008E7010008E7010008E7010008A0
:1000A000E7010008E7010008E7010008E701000890
:1000B000E7010008E7010008E7010008E701000880
:1000C000E7010008E7010008E7010008E701000870
:1000D000E7010008E7010008E7010008E701000860
:1000E000E7010008E7010008E7010008E701000850
:1000F000E7010008E7010008E7010008E701000840
:10010000E7010008E7010008E7010008E70100082F
:10011000E7010008E7010008E7010008E70100081F
:10012000E7010008E7010008E7010008E70100080F
:1001300000F002F800F03AF80AA090E8000C8244BF
:100140008344AAF10107DA4501D100F02FF8AFF29C
:10015000090EBAE80F0013F0010F18BFFB1A43F0A5
:10016000010318477804000098040000103A24BFE7
:1001700078C878C1FAD8520724BF30C830C144BF0C
:1001800004680C607047000000230024002500264E
:10019000103A28BF78C1FBD8520728BF30C148BFEA
:1001A0000B6070471FB51FBD10B510BD00F031F8D2
:1001B0001146FFF7F7FF00F0F1F900F04FF803B434
:1001C000FFF7F2FF03BC00F055F800000948804734
:1001D00009480047FEE7FEE7FEE7FEE7FEE7FEE729
:1001E000FEE7FEE7FEE7FEE704480549054A064B41
:1001F0007047000061040008310100087800002009
:1002000078060020780200207802002070477047AE
:100210007047754600F028F8AE460500694653461B
:1002200020F00700854618B020B5FFF7DDFFBDE8D8
:1002300020404FF000064FF000074FF000084FF04D
:10024000000B21F00701AC46ACE8C009ACE8C009DE
:10025000ACE8C009ACE8C0098D4670470446AFF36E
:1002600000802046FFF7ABFF0048704714000020D5
:100270007047000001491820ABBEFEE726000200CF
:1002800008B50021009103E000BF0099491C0091CE
:1002900000EB4001C1EBC011009AB2EBC10FF3D3E8
:1002A00008BD000030B10749096821F40061054A22
:1002B000116005E00349096841F40061014A1160D9
:1002C000704700000C1C01401B48806940F0100082
:1002D000194988610846806940F0800088610846B5
:1002E000806940F0010088611448006820F0706067
:1002F000124908600846006840F03060086008460F
:10030000006820F4700008600846006840F440105F
:1003100008600B48006820F47040094908600846EE
:10032000006840F4405008600648406840F440606F
:10033000044948607047000000100240001001406E
:10034000041C01400000014000B500F0EDF800F091
:100350000DF900BD10B500F001F810BD0CB500207E
:10036000019000903348006840F4803031490860C3
:1003700000BF3048006800F4003000900198401C35
:100380000190009818B90198B0F5A06FF1D12948F3
:10039000006800F4003010B10120009001E000205E
:1003A00000900098012843D12348006840F01000D5
:1003B000214908600846006820F0030008600846EC
:1003C000006840F0020008601A4840681949486017
:1003D0000846406848600846406840F480604860CD
:1003E0000846406820F47C1048600846406840F4A5
:1003F000E81048600846006840F08070086000BF60
:100400000C48006800F000700028F9D009484068E6
:1004100020F00300074948600846406840F00200A9
:10042000486000BF0348406800F00C000828F9D17C
:100430000CBD0000001002400020024030B107490E
:10044000C96841F02001054AD16005E00349C96847
:1004500021F02001014AD1607047000000100140E6
:1004600010B51348006840F00100114908600846C3
:100470004068104908400E494860084600680E4927
:1004800008400B4908600846006820F48020086096
:100490000846406820F4FE0048604FF41F00886062
:1004A000FFF758FF4FF000600449086010BD0000DE
:1004B000001002400000FFF8FFFFF6FE08ED00E02C
:1004C0001748C06940F002001549C8614720154926
:1004D000088040F2E730091D088012481038008873
:1004E00020F070000F49103908800846008840F05D
:1004F000600008800B480838008840F00100094976
:10050000083908804FF4FA7006490C310880054814
:100510002838008840F001000249283908807047D7
:1005200000100240280400400E48806944F2040193
:1005300008430C4988610C48006820F470000A499F
:1005400008600846006840F430000860084600680B
:1005500020F0706008600846006840F08060086025
:100560007047000000100240040801400949096872
:1005700009094FF4E132B1FBF2F0074A108042F270
:100580000C01121D11800021121D1180121D1180FD
:10059000704700000000002008380140FFF794FE7B
:1005A000FFF78EFFFFF7D0FE0120FFF747FF012086
:1005B000FFF778FE012400250CE00748854205D3AB
:1005C00084F001042046FFF739FF00250120FFF7E2
:1005D00057FE6D1CF1E7000020A10700FC05000894
:1005E00000000020140000006C0100081006000844
:1005F00014000020640600008801000800A24A04DC
:1006000000000000000000000102030406070809C2
:0400000508000131BD
:00000001FF
Objects/MotorControl.htm 0 → 100644
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html><head>
<title>Static Call Graph - [.\Objects\MotorControl.axf]</title></head>
<body><HR>
<H1>Static Call Graph for image .\Objects\MotorControl.axf</H1><HR>
<BR><P>#&#060CALLGRAPH&#062# ARM Linker, 5050106: Last Updated: Fri Sep 27 17:15:38 2024
<BR><P>
<H3>Maximum Stack Usage = 28 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)</H3><H3>
Call chain for Maximum Stack Depth:</H3>
SystemInit &rArr; SetSysClock &rArr; SetSysClockTo72
<P>
<H3>
Functions with no stack information
</H3><UL>
<LI><a href="#[64]">__user_initial_stackheap</a>
</UL>
</UL>
<P>
<H3>
Mutually Recursive functions
</H3> <LI><a href="#[c]">NMI_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[c]">NMI_Handler</a><BR>
<LI><a href="#[d]">HardFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[d]">HardFault_Handler</a><BR>
<LI><a href="#[e]">MemManage_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[e]">MemManage_Handler</a><BR>
<LI><a href="#[f]">BusFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[f]">BusFault_Handler</a><BR>
<LI><a href="#[10]">UsageFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[10]">UsageFault_Handler</a><BR>
<LI><a href="#[11]">SVC_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[11]">SVC_Handler</a><BR>
<LI><a href="#[12]">DebugMon_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[12]">DebugMon_Handler</a><BR>
<LI><a href="#[13]">PendSV_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[13]">PendSV_Handler</a><BR>
<LI><a href="#[14]">SysTick_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[14]">SysTick_Handler</a><BR>
<LI><a href="#[27]">ADC1_2_IRQHandler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[27]">ADC1_2_IRQHandler</a><BR>
</UL>
<P>
<H3>
Function Pointers
</H3><UL>
<LI><a href="#[27]">ADC1_2_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[44]">ADC3_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[f]">BusFault_Handler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[2a]">CAN1_RX1_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[2b]">CAN1_SCE_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[20]">DMA1_Channel1_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[21]">DMA1_Channel2_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[22]">DMA1_Channel3_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[23]">DMA1_Channel4_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[24]">DMA1_Channel5_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[25]">DMA1_Channel6_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[26]">DMA1_Channel7_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[4d]">DMA2_Channel1_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[4e]">DMA2_Channel2_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[4f]">DMA2_Channel3_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[50]">DMA2_Channel4_5_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[12]">DebugMon_Handler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[1b]">EXTI0_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[3d]">EXTI15_10_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[1c]">EXTI1_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[1d]">EXTI2_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[1e]">EXTI3_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[1f]">EXTI4_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[2c]">EXTI9_5_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[19]">FLASH_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[45]">FSMC_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[d]">HardFault_Handler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[35]">I2C1_ER_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[34]">I2C1_EV_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[37]">I2C2_ER_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[36]">I2C2_EV_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[e]">MemManage_Handler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[c]">NMI_Handler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[16]">PVD_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[13]">PendSV_Handler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[1a]">RCC_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[3e]">RTCAlarm_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[18]">RTC_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[b]">Reset_Handler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[46]">SDIO_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[38]">SPI1_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[39]">SPI2_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[48]">SPI3_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[11]">SVC_Handler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[14]">SysTick_Handler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[51]">SystemInit</a> from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_hd.o(.text)
<LI><a href="#[17]">TAMPER_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[2d]">TIM1_BRK_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[30]">TIM1_CC_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[2f]">TIM1_TRG_COM_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[2e]">TIM1_UP_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[31]">TIM2_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[32]">TIM3_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[33]">TIM4_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[47]">TIM5_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[4b]">TIM6_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[4c]">TIM7_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[40]">TIM8_BRK_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[43]">TIM8_CC_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[42]">TIM8_TRG_COM_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[41]">TIM8_UP_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[49]">UART4_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[4a]">UART5_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[3a]">USART1_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[3b]">USART2_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[3c]">USART3_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[3f]">USBWakeUp_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[28]">USB_HP_CAN1_TX_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[29]">USB_LP_CAN1_RX0_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[10]">UsageFault_Handler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[15]">WWDG_IRQHandler</a> from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET)
<LI><a href="#[53]">__main</a> from __main.o(!!!main) referenced from startup_stm32f10x_hd.o(.text)
</UL>
<P>
<H3>
Global Symbols
</H3>
<P><STRONG><a name="[53]"></a>__main</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, __main.o(!!!main))
<BR><BR>[Calls]<UL><LI><a href="#[55]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_entry
<LI><a href="#[54]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
</UL>
<P><STRONG><a name="[54]"></a>__scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter))
<BR><BR>[Called By]<UL><LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__main
</UL>
<P><STRONG><a name="[56]"></a>__scatterload_rt2</STRONG> (Thumb, 44 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
<BR><BR>[Calls]<UL><LI><a href="#[55]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_entry
</UL>
<P><STRONG><a name="[70]"></a>__scatterload_rt2_thumb_only</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
<P><STRONG><a name="[71]"></a>__scatterload_null</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
<P><STRONG><a name="[57]"></a>__scatterload_copy</STRONG> (Thumb, 26 bytes, Stack size unknown bytes, __scatter_copy.o(!!handler_copy), UNUSED)
<BR><BR>[Calls]<UL><LI><a href="#[57]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload_copy
</UL>
<BR>[Called By]<UL><LI><a href="#[57]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload_copy
</UL>
<P><STRONG><a name="[72]"></a>__scatterload_zeroinit</STRONG> (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED)
<P><STRONG><a name="[5b]"></a>__rt_lib_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit.o(.ARM.Collect$$libinit$$00000000))
<BR><BR>[Called By]<UL><LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_entry_li
</UL>
<P><STRONG><a name="[73]"></a>__rt_lib_init_alloca_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E))
<P><STRONG><a name="[74]"></a>__rt_lib_init_argv_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002C))
<P><STRONG><a name="[75]"></a>__rt_lib_init_atexit_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B))
<P><STRONG><a name="[76]"></a>__rt_lib_init_clock_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021))
<P><STRONG><a name="[77]"></a>__rt_lib_init_cpp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000032))
<P><STRONG><a name="[78]"></a>__rt_lib_init_exceptions_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030))
<P><STRONG><a name="[79]"></a>__rt_lib_init_fp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000002))
<P><STRONG><a name="[7a]"></a>__rt_lib_init_fp_trap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F))
<P><STRONG><a name="[7b]"></a>__rt_lib_init_getenv_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023))
<P><STRONG><a name="[7c]"></a>__rt_lib_init_heap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000A))
<P><STRONG><a name="[7d]"></a>__rt_lib_init_lc_collate_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000011))
<P><STRONG><a name="[7e]"></a>__rt_lib_init_lc_ctype_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013))
<P><STRONG><a name="[7f]"></a>__rt_lib_init_lc_monetary_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015))
<P><STRONG><a name="[80]"></a>__rt_lib_init_lc_numeric_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017))
<P><STRONG><a name="[81]"></a>__rt_lib_init_lc_time_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019))
<P><STRONG><a name="[82]"></a>__rt_lib_init_preinit_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000004))
<P><STRONG><a name="[83]"></a>__rt_lib_init_rand_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000E))
<P><STRONG><a name="[84]"></a>__rt_lib_init_return</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000033))
<P><STRONG><a name="[85]"></a>__rt_lib_init_signal_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D))
<P><STRONG><a name="[86]"></a>__rt_lib_init_stdio_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000025))
<P><STRONG><a name="[87]"></a>__rt_lib_init_user_alloc_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C))
<P><STRONG><a name="[60]"></a>__rt_lib_shutdown</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown.o(.ARM.Collect$$libshutdown$$00000000))
<BR><BR>[Called By]<UL><LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_exit_ls
</UL>
<P><STRONG><a name="[88]"></a>__rt_lib_shutdown_fp_trap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000006))
<P><STRONG><a name="[89]"></a>__rt_lib_shutdown_heap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E))
<P><STRONG><a name="[8a]"></a>__rt_lib_shutdown_return</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F))
<P><STRONG><a name="[8b]"></a>__rt_lib_shutdown_signal_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000009))
<P><STRONG><a name="[8c]"></a>__rt_lib_shutdown_stdio_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000003))
<P><STRONG><a name="[8d]"></a>__rt_lib_shutdown_user_alloc_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000B))
<P><STRONG><a name="[55]"></a>__rt_entry</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry.o(.ARM.Collect$$rtentry$$00000000))
<BR><BR>[Called By]<UL><LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__main
<LI><a href="#[56]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload_rt2
</UL>
<P><STRONG><a name="[8e]"></a>__rt_entry_presh_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000002))
<P><STRONG><a name="[58]"></a>__rt_entry_sh</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry4.o(.ARM.Collect$$rtentry$$00000004))
<BR><BR>[Stack]<UL><LI>Max Depth = 8 + Unknown Stack Size
<LI>Call Chain = __rt_entry_sh &rArr; __user_setup_stackheap
</UL>
<BR>[Calls]<UL><LI><a href="#[59]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__user_setup_stackheap
</UL>
<P><STRONG><a name="[5a]"></a>__rt_entry_li</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000A))
<BR><BR>[Calls]<UL><LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_lib_init
</UL>
<P><STRONG><a name="[8f]"></a>__rt_entry_postsh_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000009))
<P><STRONG><a name="[5c]"></a>__rt_entry_main</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000D))
<BR><BR>[Stack]<UL><LI>Max Depth = 8 + Unknown Stack Size
<LI>Call Chain = __rt_entry_main &rArr; main &rArr; Delay
</UL>
<BR>[Calls]<UL><LI><a href="#[5d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
<LI><a href="#[5e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;exit
</UL>
<P><STRONG><a name="[90]"></a>__rt_entry_postli_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000C))
<P><STRONG><a name="[65]"></a>__rt_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit.o(.ARM.Collect$$rtexit$$00000000))
<BR><BR>[Called By]<UL><LI><a href="#[5e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;exit
</UL>
<P><STRONG><a name="[5f]"></a>__rt_exit_ls</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000003))
<BR><BR>[Calls]<UL><LI><a href="#[60]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_lib_shutdown
</UL>
<P><STRONG><a name="[91]"></a>__rt_exit_prels_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002))
<P><STRONG><a name="[61]"></a>__rt_exit_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000004))
<BR><BR>[Calls]<UL><LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_sys_exit
</UL>
<P><STRONG><a name="[b]"></a>Reset_Handler</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[c]"></a>NMI_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NMI_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NMI_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[d]"></a>HardFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[e]"></a>MemManage_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MemManage_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MemManage_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[f]"></a>BusFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BusFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BusFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[10]"></a>UsageFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[10]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UsageFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[10]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UsageFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[11]"></a>SVC_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[11]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SVC_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[11]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SVC_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[12]"></a>DebugMon_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[12]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DebugMon_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[12]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DebugMon_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[13]"></a>PendSV_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[13]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;PendSV_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[13]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;PendSV_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[14]"></a>SysTick_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[14]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SysTick_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[14]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SysTick_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[27]"></a>ADC1_2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[27]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC1_2_IRQHandler
</UL>
<BR>[Called By]<UL><LI><a href="#[27]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC1_2_IRQHandler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[44]"></a>ADC3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[2a]"></a>CAN1_RX1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[2b]"></a>CAN1_SCE_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[20]"></a>DMA1_Channel1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[21]"></a>DMA1_Channel2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[22]"></a>DMA1_Channel3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[23]"></a>DMA1_Channel4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[24]"></a>DMA1_Channel5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[25]"></a>DMA1_Channel6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[26]"></a>DMA1_Channel7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[4d]"></a>DMA2_Channel1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[4e]"></a>DMA2_Channel2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[4f]"></a>DMA2_Channel3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[50]"></a>DMA2_Channel4_5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[1b]"></a>EXTI0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[3d]"></a>EXTI15_10_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[1c]"></a>EXTI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[1d]"></a>EXTI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[1e]"></a>EXTI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[1f]"></a>EXTI4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[2c]"></a>EXTI9_5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[19]"></a>FLASH_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[45]"></a>FSMC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[35]"></a>I2C1_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[34]"></a>I2C1_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[37]"></a>I2C2_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[36]"></a>I2C2_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[16]"></a>PVD_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[1a]"></a>RCC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[3e]"></a>RTCAlarm_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[18]"></a>RTC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[46]"></a>SDIO_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[38]"></a>SPI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[39]"></a>SPI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[48]"></a>SPI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[17]"></a>TAMPER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[2d]"></a>TIM1_BRK_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[30]"></a>TIM1_CC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[2f]"></a>TIM1_TRG_COM_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[2e]"></a>TIM1_UP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[31]"></a>TIM2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[32]"></a>TIM3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[33]"></a>TIM4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[47]"></a>TIM5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[4b]"></a>TIM6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[4c]"></a>TIM7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[40]"></a>TIM8_BRK_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[43]"></a>TIM8_CC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[42]"></a>TIM8_TRG_COM_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[41]"></a>TIM8_UP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[49]"></a>UART4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[4a]"></a>UART5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[3a]"></a>USART1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[3b]"></a>USART2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[3c]"></a>USART3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[3f]"></a>USBWakeUp_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[28]"></a>USB_HP_CAN1_TX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[29]"></a>USB_LP_CAN1_RX0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[15]"></a>WWDG_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(RESET)
</UL>
<P><STRONG><a name="[64]"></a>__user_initial_stackheap</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, startup_stm32f10x_hd.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[59]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__user_setup_stackheap
</UL>
<P><STRONG><a name="[92]"></a>__use_two_region_memory</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
<P><STRONG><a name="[8]"></a>__rt_heap_escrow</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
<P><STRONG><a name="[7]"></a>__rt_heap_expand</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
<P><STRONG><a name="[59]"></a>__user_setup_stackheap</STRONG> (Thumb, 74 bytes, Stack size 8 bytes, sys_stackheap_outer.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 8 + Unknown Stack Size
<LI>Call Chain = __user_setup_stackheap
</UL>
<BR>[Calls]<UL><LI><a href="#[64]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__user_initial_stackheap
<LI><a href="#[63]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__user_perproc_libspace
</UL>
<BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_entry_sh
</UL>
<P><STRONG><a name="[5e]"></a>exit</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, exit.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_exit
</UL>
<BR>[Called By]<UL><LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_entry_main
</UL>
<P><STRONG><a name="[93]"></a>__user_libspace</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
<P><STRONG><a name="[63]"></a>__user_perproc_libspace</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[59]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__user_setup_stackheap
</UL>
<P><STRONG><a name="[94]"></a>__user_perthread_libspace</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
<P><STRONG><a name="[95]"></a>__I$use$semihosting</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
<P><STRONG><a name="[96]"></a>__use_no_semihosting_swi</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
<P><STRONG><a name="[97]"></a>__semihosting_library_function</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, indicate_semi.o(.text), UNUSED)
<P><STRONG><a name="[62]"></a>_sys_exit</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, sys_exit.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[61]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_exit_exit
</UL>
<P><STRONG><a name="[6f]"></a>Delay</STRONG> (Thumb, 34 bytes, Stack size 8 bytes, main.o(i.Delay))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = Delay
</UL>
<BR>[Called By]<UL><LI><a href="#[5d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<P><STRONG><a name="[6e]"></a>Enable_Stepper</STRONG> (Thumb, 30 bytes, Stack size 0 bytes, main.o(i.Enable_Stepper))
<BR><BR>[Called By]<UL><LI><a href="#[5d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<P><STRONG><a name="[6b]"></a>GPIO_Init</STRONG> (Thumb, 110 bytes, Stack size 0 bytes, main.o(i.GPIO_Init))
<BR><BR>[Called By]<UL><LI><a href="#[5d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<P><STRONG><a name="[66]"></a>Serial_Init</STRONG> (Thumb, 12 bytes, Stack size 4 bytes, uart_log.o(i.Serial_Init))
<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = Serial_Init
</UL>
<BR>[Calls]<UL><LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;USART1_Init
<LI><a href="#[67]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;USART1_GPIO_Init
</UL>
<BR>[Called By]<UL><LI><a href="#[5d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<P><STRONG><a name="[6d]"></a>Set_Direction</STRONG> (Thumb, 30 bytes, Stack size 0 bytes, main.o(i.Set_Direction))
<BR><BR>[Called By]<UL><LI><a href="#[5d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<P><STRONG><a name="[51]"></a>SystemInit</STRONG> (Thumb, 78 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit))
<BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = SystemInit &rArr; SetSysClock &rArr; SetSysClockTo72
</UL>
<BR>[Calls]<UL><LI><a href="#[69]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SetSysClock
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f10x_hd.o(.text)
</UL>
<P><STRONG><a name="[6c]"></a>TIM3_Init</STRONG> (Thumb, 96 bytes, Stack size 0 bytes, main.o(i.TIM3_Init))
<BR><BR>[Called By]<UL><LI><a href="#[5d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<P><STRONG><a name="[67]"></a>USART1_GPIO_Init</STRONG> (Thumb, 58 bytes, Stack size 0 bytes, uart_log.o(i.USART1_GPIO_Init))
<BR><BR>[Called By]<UL><LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Serial_Init
</UL>
<P><STRONG><a name="[68]"></a>USART1_Init</STRONG> (Thumb, 38 bytes, Stack size 0 bytes, uart_log.o(i.USART1_Init))
<BR><BR>[Called By]<UL><LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Serial_Init
</UL>
<P><STRONG><a name="[5d]"></a>main</STRONG> (Thumb, 58 bytes, Stack size 0 bytes, main.o(i.main))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = main &rArr; Delay
</UL>
<BR>[Calls]<UL><LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Serial_Init
<LI><a href="#[6c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM3_Init
<LI><a href="#[6d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Set_Direction
<LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_Init
<LI><a href="#[6e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Enable_Stepper
<LI><a href="#[6f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Delay
</UL>
<BR>[Called By]<UL><LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_entry_main
</UL>
<P>
<H3>
Local Symbols
</H3>
<P><STRONG><a name="[69]"></a>SetSysClock</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SetSysClock))
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = SetSysClock &rArr; SetSysClockTo72
</UL>
<BR>[Calls]<UL><LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SetSysClockTo72
</UL>
<BR>[Called By]<UL><LI><a href="#[51]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemInit
</UL>
<P><STRONG><a name="[6a]"></a>SetSysClockTo72</STRONG> (Thumb, 214 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72))
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = SetSysClockTo72
</UL>
<BR>[Called By]<UL><LI><a href="#[69]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SetSysClock
</UL>
<P>
<H3>
Undefined Global Symbols
</H3><HR></body></html>
Objects/MotorControl.lnp 0 → 100644
--cpu Cortex-M3
".\objects\main.o"
".\objects\uart_log.o"
".\objects\step_motor.o"
".\objects\startup_stm32f10x_hd.o"
".\objects\system_stm32f10x.o"
--strict --scatter ".\Objects\MotorControl.sct"
-u _printf --summary_stderr --info summarysizes --map --xref --callgraph --symbols
--info sizes --info totals --info unused --info veneers
--list ".\Listings\MotorControl.map" -o .\Objects\MotorControl.axf
\ No newline at end of file
Objects/MotorControl.sct 0 → 100644
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00010000 { ; RW data
.ANY (+RW +ZI)
}
}
Objects/MotorControl_PWM.dep 0 → 100644
Dependencies for Project 'MotorControl', Target 'PWM': (DO NOT MODIFY !)
F (.\main.c)(0x66F677B1)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -IC:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include -IC:\Keil_v5\ARM\CMSIS\Include -I.\Module\Inc --locale=english --c99 -I D:\Ƕʽ\mcu\Motor_Control\RTE -I D:\Ƕʽ\mcu\Motor_Control\RTE\Device\STM32F103ZE -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1 -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1\Device\Include -I C:\Keil_v5\ARM\CMSIS\Include -D__UVISION_VERSION="514" -D_RTE_ -DSTM32F10X_HD -o .\objects\main.o --omf_browse .\objects\main.crf --depend .\objects\main.d)
I (C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h)(0x5825386C)
I (D:\嵌入式\mcu\Motor_Control\RTE\RTE_Components.h)(0x00000000)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cm3.h)(0x5714AE54)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5475F300)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cmInstr.h)(0x5714AE54)
I (C:\Keil_v5\ARM\CMSIS\Include\cmsis_armcc.h)(0x5714AE54)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cmFunc.h)(0x5714AE54)
I (C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h)(0x5825386C)
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x5475F300)
I (.\Module\Inc\uart_log.h)(0x66F3E910)
F (.\Module\Inc\uart_log.h)(0x66F3E910)()
F (.\Module\Src\uart_log.c)(0x66F6776B)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -IC:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include -IC:\Keil_v5\ARM\CMSIS\Include -I.\Module\Inc --locale=english --c99 -I D:\Ƕʽ\mcu\Motor_Control\RTE -I D:\Ƕʽ\mcu\Motor_Control\RTE\Device\STM32F103ZE -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1 -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1\Device\Include -I C:\Keil_v5\ARM\CMSIS\Include -D__UVISION_VERSION="514" -D_RTE_ -DSTM32F10X_HD -o .\objects\uart_log.o --omf_browse .\objects\uart_log.crf --depend .\objects\uart_log.d)
I (.\Module\Inc\uart_log.h)(0x66F3E910)
I (C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h)(0x5825386C)
I (D:\嵌入式\mcu\Motor_Control\RTE\RTE_Components.h)(0x00000000)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cm3.h)(0x5714AE54)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5475F300)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cmInstr.h)(0x5714AE54)
I (C:\Keil_v5\ARM\CMSIS\Include\cmsis_armcc.h)(0x5714AE54)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cmFunc.h)(0x5714AE54)
I (C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h)(0x5825386C)
I (C:\Keil_v5\ARM\ARMCC\include\stdarg.h)(0x5475F2FA)
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x5475F300)
I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x5475F300)
F (.\Module\Inc\step_motor.h)(0x66F67758)()
F (.\Module\Src\step_motor.c)(0x66F67758)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -IC:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include -IC:\Keil_v5\ARM\CMSIS\Include -I.\Module\Inc --locale=english --c99 -I D:\Ƕʽ\mcu\Motor_Control\RTE -I D:\Ƕʽ\mcu\Motor_Control\RTE\Device\STM32F103ZE -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1 -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1\Device\Include -I C:\Keil_v5\ARM\CMSIS\Include -D__UVISION_VERSION="514" -D_RTE_ -DSTM32F10X_HD -o .\objects\step_motor.o --omf_browse .\objects\step_motor.crf --depend .\objects\step_motor.d)
F (RTE\Device\STM32F103ZE\RTE_Device.h)(0x5FC04FEA)()
F (RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s)(0x61AD795E)(--cpu Cortex-M3 -g --apcs=interwork -I D:\Ƕʽ\mcu\Motor_Control\RTE -I D:\Ƕʽ\mcu\Motor_Control\RTE\Device\STM32F103ZE -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1 -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1\Device\Include -I C:\Keil_v5\ARM\CMSIS\Include --pd "__UVISION_VERSION SETA 514" --pd "_RTE_ SETA 1" --pd "STM32F10X_HD SETA 1" --list .\listings\startup_stm32f10x_hd.lst --xref -o .\objects\startup_stm32f10x_hd.o --depend .\objects\startup_stm32f10x_hd.d)
F (RTE\Device\STM32F103ZE\system_stm32f10x.c)(0x61AD795E)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -IC:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include -IC:\Keil_v5\ARM\CMSIS\Include -I.\Module\Inc --locale=english --c99 -I D:\Ƕʽ\mcu\Motor_Control\RTE -I D:\Ƕʽ\mcu\Motor_Control\RTE\Device\STM32F103ZE -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1 -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1\Device\Include -I C:\Keil_v5\ARM\CMSIS\Include -D__UVISION_VERSION="514" -D_RTE_ -DSTM32F10X_HD -o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d)
I (C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h)(0x5825386C)
I (D:\嵌入式\mcu\Motor_Control\RTE\RTE_Components.h)(0x00000000)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cm3.h)(0x5714AE54)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5475F300)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cmInstr.h)(0x5714AE54)
I (C:\Keil_v5\ARM\CMSIS\Include\cmsis_armcc.h)(0x5714AE54)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cmFunc.h)(0x5714AE54)
I (C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h)(0x5825386C)
Objects/MotorControl_Target 1.dep 0 → 100644
Dependencies for Project 'MotorControl', Target 'Target 1': (DO NOT MODIFY !)
F (.\main.c)(0x66F3DF7C)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -IC:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include -IC:\Keil_v5\ARM\CMSIS\Include --locale=english --c99 -I D:\Ƕʽ\mcu\Motor_Control\RTE -I D:\Ƕʽ\mcu\Motor_Control\RTE\Device\STM32F103ZE -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1 -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1\Device\Include -I C:\Keil_v5\ARM\CMSIS\Include -D__UVISION_VERSION="514" -D_RTE_ -DSTM32F10X_HD -o .\objects\main.o --omf_browse .\objects\main.crf --depend .\objects\main.d)
I (C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h)(0x5825386C)
I (D:\嵌入式\mcu\Motor_Control\RTE\RTE_Components.h)(0x00000000)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cm3.h)(0x5714AE54)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5475F300)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cmInstr.h)(0x5714AE54)
I (C:\Keil_v5\ARM\CMSIS\Include\cmsis_armcc.h)(0x5714AE54)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cmFunc.h)(0x5714AE54)
I (C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h)(0x5825386C)
I (C:\Keil_v5\ARM\ARMCC\include\stdbool.h)(0x5475F300)
I (uart_log.h)(0x66F3E19A)
F (.\StepMotor.h)(0x66F28B19)()
F (.\StepMotor.c)(0x66F28C69)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -IC:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include -IC:\Keil_v5\ARM\CMSIS\Include --locale=english --c99 -I D:\Ƕʽ\mcu\Motor_Control\RTE -I D:\Ƕʽ\mcu\Motor_Control\RTE\Device\STM32F103ZE -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1 -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1\Device\Include -I C:\Keil_v5\ARM\CMSIS\Include -D__UVISION_VERSION="514" -D_RTE_ -DSTM32F10X_HD -o .\objects\stepmotor.o --omf_browse .\objects\stepmotor.crf --depend .\objects\stepmotor.d)
F (.\uart_log.h)(0x66F3E19A)()
F (.\uart_log.c)(0x66F3E28E)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -IC:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include -IC:\Keil_v5\ARM\CMSIS\Include --locale=english --c99 -I D:\Ƕʽ\mcu\Motor_Control\RTE -I D:\Ƕʽ\mcu\Motor_Control\RTE\Device\STM32F103ZE -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1 -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1\Device\Include -I C:\Keil_v5\ARM\CMSIS\Include -D__UVISION_VERSION="514" -D_RTE_ -DSTM32F10X_HD -o .\objects\uart_log.o --omf_browse .\objects\uart_log.crf --depend .\objects\uart_log.d)
I (uart_log.h)(0x66F3E19A)
I (C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h)(0x5825386C)
I (D:\嵌入式\mcu\Motor_Control\RTE\RTE_Components.h)(0x00000000)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cm3.h)(0x5714AE54)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5475F300)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cmInstr.h)(0x5714AE54)
I (C:\Keil_v5\ARM\CMSIS\Include\cmsis_armcc.h)(0x5714AE54)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cmFunc.h)(0x5714AE54)
I (C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h)(0x5825386C)
I (C:\Keil_v5\ARM\ARMCC\include\stdarg.h)(0x5475F2FA)
I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x5475F300)
I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x5475F300)
F (RTE\Device\STM32F103ZE\RTE_Device.h)(0x5FC04FEA)()
F (RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s)(0x61AD795E)(--cpu Cortex-M3 -g --apcs=interwork -I D:\Ƕʽ\mcu\Motor_Control\RTE -I D:\Ƕʽ\mcu\Motor_Control\RTE\Device\STM32F103ZE -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1 -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1\Device\Include -I C:\Keil_v5\ARM\CMSIS\Include --pd "__UVISION_VERSION SETA 514" --pd "_RTE_ SETA 1" --pd "STM32F10X_HD SETA 1" --list .\listings\startup_stm32f10x_hd.lst --xref -o .\objects\startup_stm32f10x_hd.o --depend .\objects\startup_stm32f10x_hd.d)
F (RTE\Device\STM32F103ZE\system_stm32f10x.c)(0x61AD795E)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork --split_sections -IC:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include -IC:\Keil_v5\ARM\CMSIS\Include --locale=english --c99 -I D:\Ƕʽ\mcu\Motor_Control\RTE -I D:\Ƕʽ\mcu\Motor_Control\RTE\Device\STM32F103ZE -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1 -I C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.4.1\Device\Include -I C:\Keil_v5\ARM\CMSIS\Include -D__UVISION_VERSION="514" -D_RTE_ -DSTM32F10X_HD -o .\objects\system_stm32f10x.o --omf_browse .\objects\system_stm32f10x.crf --depend .\objects\system_stm32f10x.d)
I (C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h)(0x5825386C)
I (D:\嵌入式\mcu\Motor_Control\RTE\RTE_Components.h)(0x00000000)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cm3.h)(0x5714AE54)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5475F300)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cmInstr.h)(0x5714AE54)
I (C:\Keil_v5\ARM\CMSIS\Include\cmsis_armcc.h)(0x5714AE54)
I (C:\Keil_v5\ARM\CMSIS\Include\core_cmFunc.h)(0x5714AE54)
I (C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h)(0x5825386C)
Objects/main.d 0 → 100644
.\objects\main.o: main.c
.\objects\main.o: C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h
.\objects\main.o: D:\嵌入式\mcu\Motor_Control\RTE\RTE_Components.h
.\objects\main.o: C:\Keil_v5\ARM\CMSIS\Include\core_cm3.h
.\objects\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\main.o: C:\Keil_v5\ARM\CMSIS\Include\core_cmInstr.h
.\objects\main.o: C:\Keil_v5\ARM\CMSIS\Include\cmsis_armcc.h
.\objects\main.o: C:\Keil_v5\ARM\CMSIS\Include\core_cmFunc.h
.\objects\main.o: C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h
.\objects\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdbool.h
.\objects\main.o: .\Module\Inc\uart_log.h
Objects/main.o 0 → 100644
File added
Objects/startup_stm32f10x_hd.d 0 → 100644
.\objects\startup_stm32f10x_hd.o: RTE\Device\STM32F103ZE\startup_stm32f10x_hd.s
Objects/step_motor.d 0 → 100644
.\objects\step_motor.o: Module\Src\step_motor.c
Objects/stepmotor.d 0 → 100644
.\objects\stepmotor.o: StepMotor.c
Objects/system_stm32f10x.d 0 → 100644
.\objects\system_stm32f10x.o: RTE\Device\STM32F103ZE\system_stm32f10x.c
.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h
.\objects\system_stm32f10x.o: D:\嵌入式\mcu\Motor_Control\RTE\RTE_Components.h
.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\CMSIS\Include\core_cm3.h
.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\CMSIS\Include\core_cmInstr.h
.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\CMSIS\Include\cmsis_armcc.h
.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\CMSIS\Include\core_cmFunc.h
.\objects\system_stm32f10x.o: C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h
Objects/uart_log.d 0 → 100644
.\objects\uart_log.o: Module\Src\uart_log.c
.\objects\uart_log.o: .\Module\Inc\uart_log.h
.\objects\uart_log.o: C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\stm32f10x.h
.\objects\uart_log.o: D:\嵌入式\mcu\Motor_Control\RTE\RTE_Components.h
.\objects\uart_log.o: C:\Keil_v5\ARM\CMSIS\Include\core_cm3.h
.\objects\uart_log.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\uart_log.o: C:\Keil_v5\ARM\CMSIS\Include\core_cmInstr.h
.\objects\uart_log.o: C:\Keil_v5\ARM\CMSIS\Include\cmsis_armcc.h
.\objects\uart_log.o: C:\Keil_v5\ARM\CMSIS\Include\core_cmFunc.h
.\objects\uart_log.o: C:\Keil_v5\ARM\Pack\Keil\STM32F1xx_DFP\2.2.0\Device\Include\system_stm32f10x.h
.\objects\uart_log.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdarg.h
.\objects\uart_log.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
.\objects\uart_log.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
RTE/Device/STM32F103ZE/RTE_Device.h 0 → 100644
/* -----------------------------------------------------------------------------
* Copyright (c) 2013-2016 Arm Limited (or its affiliates). All
* rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*
* $Date: 09. September 2016
* $Revision: V1.1.2
*
* Project: RTE Device Configuration for STMicroelectronics STM32F1xx
*
* -------------------------------------------------------------------------- */
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
#ifndef __RTE_DEVICE_H
#define __RTE_DEVICE_H
#define GPIO_PORT(num) \
((num == 0) ? GPIOA : \
(num == 1) ? GPIOB : \
(num == 2) ? GPIOC : \
(num == 3) ? GPIOD : \
(num == 4) ? GPIOE : \
(num == 5) ? GPIOF : \
(num == 6) ? GPIOG : \
NULL)
// <h> Clock Configuration
// <o> High-speed Internal Clock <1-999999999>
#define RTE_HSI 8000000
// <o> High-speed External Clock <1-999999999>
#define RTE_HSE 25000000
// <o> System Clock <1-999999999>
#define RTE_SYSCLK 72000000
// <o> HCLK Clock <1-999999999>
#define RTE_HCLK 72000000
// <o> APB1 Clock <1-999999999>
#define RTE_PCLK1 36000000
// <o> APB2 Clock <1-999999999>
#define RTE_PCLK2 72000000
// <o> ADC Clock <1-999999999>
#define RTE_ADCCLK 36000000
// USB Clock
#define RTE_USBCLK 48000000
// </h>
// <e> USART1 (Universal synchronous asynchronous receiver transmitter)
// <i> Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART
#define RTE_USART1 0
// <o> USART1_TX Pin <0=>Not Used <1=>PA9
#define RTE_USART1_TX_PORT_ID_DEF 0
#if (RTE_USART1_TX_PORT_ID_DEF == 0)
#define RTE_USART1_TX_DEF 0
#elif (RTE_USART1_TX_PORT_ID_DEF == 1)
#define RTE_USART1_TX_DEF 1
#define RTE_USART1_TX_PORT_DEF GPIOA
#define RTE_USART1_TX_BIT_DEF 9
#else
#error "Invalid USART1_TX Pin Configuration!"
#endif
// <o> USART1_RX Pin <0=>Not Used <1=>PA10
#define RTE_USART1_RX_PORT_ID_DEF 0
#if (RTE_USART1_RX_PORT_ID_DEF == 0)
#define RTE_USART1_RX_DEF 0
#elif (RTE_USART1_RX_PORT_ID_DEF == 1)
#define RTE_USART1_RX_DEF 1
#define RTE_USART1_RX_PORT_DEF GPIOA
#define RTE_USART1_RX_BIT_DEF 10
#else
#error "Invalid USART1_RX Pin Configuration!"
#endif
// <o> USART1_CK Pin <0=>Not Used <1=>PA8
#define RTE_USART1_CK_PORT_ID_DEF 0
#if (RTE_USART1_CK_PORT_ID_DEF == 0)
#define RTE_USART1_CK 0
#elif (RTE_USART1_CK_PORT_ID_DEF == 1)
#define RTE_USART1_CK 1
#define RTE_USART1_CK_PORT_DEF GPIOA
#define RTE_USART1_CK_BIT_DEF 8
#else
#error "Invalid USART1_CK Pin Configuration!"
#endif
// <o> USART1_CTS Pin <0=>Not Used <1=>PA11
#define RTE_USART1_CTS_PORT_ID_DEF 0
#if (RTE_USART1_CTS_PORT_ID_DEF == 0)
#define RTE_USART1_CTS 0
#elif (RTE_USART1_CTS_PORT_ID_DEF == 1)
#define RTE_USART1_CTS 1
#define RTE_USART1_CTS_PORT_DEF GPIOA
#define RTE_USART1_CTS_BIT_DEF 11
#else
#error "Invalid USART1_CTS Pin Configuration!"
#endif
// <o> USART1_RTS Pin <0=>Not Used <1=>PA12
#define RTE_USART1_RTS_PORT_ID_DEF 0
#if (RTE_USART1_RTS_PORT_ID_DEF == 0)
#define RTE_USART1_RTS 0
#elif (RTE_USART1_RTS_PORT_ID_DEF == 1)
#define RTE_USART1_RTS 1
#define RTE_USART1_RTS_PORT_DEF GPIOA
#define RTE_USART1_RTS_BIT_DEF 12
#else
#error "Invalid USART1_RTS Pin Configuration!"
#endif
// <e> USART1 Pin Remap
// <i> Enable USART1 Pin Remapping
#define RTE_USART1_REMAP_FULL 0
// <o> USART1_TX Pin <0=>Not Used <1=>PB6
#define RTE_USART1_TX_PORT_ID_FULL 0
#if (RTE_USART1_TX_PORT_ID_FULL == 0)
#define RTE_USART1_TX_FULL 0
#elif (RTE_USART1_TX_PORT_ID_FULL == 1)
#define RTE_USART1_TX_FULL 1
#define RTE_USART1_TX_PORT_FULL GPIOB
#define RTE_USART1_TX_BIT_FULL 6
#else
#error "Invalid USART1_TX Pin Configuration!"
#endif
// <o> USART1_RX Pin <0=>Not Used <1=>PB7
#define RTE_USART1_RX_PORT_ID_FULL 0
#if (RTE_USART1_RX_PORT_ID_FULL == 0)
#define RTE_USART1_RX_FULL 0
#elif (RTE_USART1_RX_PORT_ID_FULL == 1)
#define RTE_USART1_RX_FULL 1
#define RTE_USART1_RX_PORT_FULL GPIOB
#define RTE_USART1_RX_BIT_FULL 7
#else
#error "Invalid USART1_RX Pin Configuration!"
#endif
// </e>
#if (RTE_USART1_REMAP_FULL)
#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP
#define RTE_USART1_TX RTE_USART1_TX_FULL
#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL
#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL
#define RTE_USART1_RX RTE_USART1_RX_FULL
#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL
#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL
#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF
#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF
#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF
#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF
#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF
#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF
#else
#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP
#define RTE_USART1_TX RTE_USART1_TX_DEF
#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF
#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF
#define RTE_USART1_RX RTE_USART1_RX_DEF
#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF
#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF
#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF
#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF
#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF
#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF
#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF
#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF
#endif
// <e> DMA Rx
// <o1> Number <1=>1
// <i> Selects DMA Number (only DMA1 can be used)
// <o2> Channel <5=>5
// <i> Selects DMA Channel (only Channel 5 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
// <i> Set DMA Channel priority
// </e>
#define RTE_USART1_RX_DMA 0
#define RTE_USART1_RX_DMA_NUMBER 1
#define RTE_USART1_RX_DMA_CHANNEL 5
#define RTE_USART1_RX_DMA_PRIORITY 0
// <e> DMA Tx
// <o1> Number <1=>1
// <i> Selects DMA Number (only DMA1 can be used)
// <o2> Channel <4=>4
// <i> Selects DMA Channel (only Channel 4 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
// <i> Set DMA Channel priority
// </e>
#define RTE_USART1_TX_DMA 0
#define RTE_USART1_TX_DMA_NUMBER 1
#define RTE_USART1_TX_DMA_CHANNEL 4
#define RTE_USART1_TX_DMA_PRIORITY 0
// </e>
// <e> USART2 (Universal synchronous asynchronous receiver transmitter)
// <i> Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART
#define RTE_USART2 0
// <o> USART2_TX Pin <0=>Not Used <1=>PA2
#define RTE_USART2_TX_PORT_ID_DEF 0
#if (RTE_USART2_TX_PORT_ID_DEF == 0)
#define RTE_USART2_TX_DEF 0
#elif (RTE_USART2_TX_PORT_ID_DEF == 1)
#define RTE_USART2_TX_DEF 1
#define RTE_USART2_TX_PORT_DEF GPIOA
#define RTE_USART2_TX_BIT_DEF 2
#else
#error "Invalid USART2_TX Pin Configuration!"
#endif
// <o> USART2_RX Pin <0=>Not Used <1=>PA3
#define RTE_USART2_RX_PORT_ID_DEF 0
#if (RTE_USART2_RX_PORT_ID_DEF == 0)
#define RTE_USART2_RX_DEF 0
#elif (RTE_USART2_RX_PORT_ID_DEF == 1)
#define RTE_USART2_RX_DEF 1
#define RTE_USART2_RX_PORT_DEF GPIOA
#define RTE_USART2_RX_BIT_DEF 3
#else
#error "Invalid USART2_RX Pin Configuration!"
#endif
// <o> USART2_CK Pin <0=>Not Used <1=>PA4
#define RTE_USART2_CK_PORT_ID_DEF 0
#if (RTE_USART2_CK_PORT_ID_DEF == 0)
#define RTE_USART2_CK_DEF 0
#elif (RTE_USART2_CK_PORT_ID_DEF == 1)
#define RTE_USART2_CK_DEF 1
#define RTE_USART2_CK_PORT_DEF GPIOA
#define RTE_USART2_CK_BIT_DEF 4
#else
#error "Invalid USART2_CK Pin Configuration!"
#endif
// <o> USART2_CTS Pin <0=>Not Used <1=>PA0
#define RTE_USART2_CTS_PORT_ID_DEF 0
#if (RTE_USART2_CTS_PORT_ID_DEF == 0)
#define RTE_USART2_CTS_DEF 0
#elif (RTE_USART2_CTS_PORT_ID_DEF == 1)
#define RTE_USART2_CTS_DEF 1
#define RTE_USART2_CTS_PORT_DEF GPIOA
#define RTE_USART2_CTS_BIT_DEF 0
#else
#error "Invalid USART2_CTS Pin Configuration!"
#endif
// <o> USART2_RTS Pin <0=>Not Used <1=>PA1
#define RTE_USART2_RTS_PORT_ID_DEF 0
#if (RTE_USART2_RTS_PORT_ID_DEF == 0)
#define RTE_USART2_RTS_DEF 0
#elif (RTE_USART2_RTS_PORT_ID_DEF == 1)
#define RTE_USART2_RTS_DEF 1
#define RTE_USART2_RTS_PORT_DEF GPIOA
#define RTE_USART2_RTS_BIT_DEF 1
#else
#error "Invalid USART2_RTS Pin Configuration!"
#endif
// <e> USART2 Pin Remap
// <i> Enable USART2 Pin Remapping
#define RTE_USART2_REMAP_FULL 0
// <o> USART2_TX Pin <0=>Not Used <1=>PD5
#define RTE_USART2_TX_PORT_ID_FULL 0
#if (RTE_USART2_TX_PORT_ID_FULL == 0)
#define RTE_USART2_TX_FULL 0
#elif (RTE_USART2_TX_PORT_ID_FULL == 1)
#define RTE_USART2_TX_FULL 1
#define RTE_USART2_TX_PORT_FULL GPIOD
#define RTE_USART2_TX_BIT_FULL 5
#else
#error "Invalid USART2_TX Pin Configuration!"
#endif
// <o> USART2_RX Pin <0=>Not Used <1=>PD6
#define RTE_USART2_RX_PORT_ID_FULL 0
#if (RTE_USART2_RX_PORT_ID_FULL == 0)
#define RTE_USART2_RX_FULL 0
#elif (RTE_USART2_RX_PORT_ID_FULL == 1)
#define RTE_USART2_RX_FULL 1
#define RTE_USART2_RX_PORT_FULL GPIOD
#define RTE_USART2_RX_BIT_FULL 6
#else
#error "Invalid USART2_RX Pin Configuration!"
#endif
// <o> USART2_CK Pin <0=>Not Used <1=>PD7
#define RTE_USART2_CK_PORT_ID_FULL 0
#if (RTE_USART2_CK_PORT_ID_FULL == 0)
#define RTE_USART2_CK_FULL 0
#elif (RTE_USART2_CK_PORT_ID_FULL == 1)
#define RTE_USART2_CK_FULL 1
#define RTE_USART2_CK_PORT_FULL GPIOD
#define RTE_USART2_CK_BIT_FULL 7
#else
#error "Invalid USART2_CK Pin Configuration!"
#endif
// <o> USART2_CTS Pin <0=>Not Used <1=>PD3
#define RTE_USART2_CTS_PORT_ID_FULL 0
#if (RTE_USART2_CTS_PORT_ID_FULL == 0)
#define RTE_USART2_CTS_FULL 0
#elif (RTE_USART2_CTS_PORT_ID_FULL == 1)
#define RTE_USART2_CTS_FULL 1
#define RTE_USART2_CTS_PORT_FULL GPIOD
#define RTE_USART2_CTS_BIT_FULL 3
#else
#error "Invalid USART2_CTS Pin Configuration!"
#endif
// <o> USART2_RTS Pin <0=>Not Used <1=>PD4
#define RTE_USART2_RTS_PORT_ID_FULL 0
#if (RTE_USART2_RTS_PORT_ID_FULL == 0)
#define RTE_USART2_RTS_FULL 0
#elif (RTE_USART2_RTS_PORT_ID_FULL == 1)
#define RTE_USART2_RTS_FULL 1
#define RTE_USART2_RTS_PORT_FULL GPIOD
#define RTE_USART2_RTS_BIT_FULL 4
#else
#error "Invalid USART2_RTS Pin Configuration!"
#endif
// </e>
#if (RTE_USART2_REMAP_FULL)
#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP
#define RTE_USART2_TX RTE_USART2_TX_FULL
#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL
#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL
#define RTE_USART2_RX RTE_USART2_RX_FULL
#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL
#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL
#define RTE_USART2_CK RTE_USART2_CK_FULL
#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL
#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL
#define RTE_USART2_CTS RTE_USART2_CTS_FULL
#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL
#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL
#define RTE_USART2_RTS RTE_USART2_RTS_FULL
#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL
#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL
#else
#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP
#define RTE_USART2_TX RTE_USART2_TX_DEF
#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF
#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF
#define RTE_USART2_RX RTE_USART2_RX_DEF
#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF
#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF
#define RTE_USART2_CK RTE_USART2_CK_DEF
#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF
#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF
#define RTE_USART2_CTS RTE_USART2_CTS_DEF
#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF
#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF
#define RTE_USART2_RTS RTE_USART2_RTS_DEF
#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF
#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF
#endif
// <e> DMA Rx
// <o1> Number <1=>1
// <i> Selects DMA Number (only DMA1 can be used)
// <o2> Channel <6=>6
// <i> Selects DMA Channel (only Channel 6 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
// <i> Set DMA Channel priority
// </e>
#define RTE_USART2_RX_DMA 0
#define RTE_USART2_RX_DMA_NUMBER 1
#define RTE_USART2_RX_DMA_CHANNEL 6
#define RTE_USART2_RX_DMA_PRIORITY 0
// <e> DMA Tx
// <o1> Number <1=>1
// <i> Selects DMA Number (only DMA1 can be used)
// <o2> Channel <7=>7
// <i> Selects DMA Channel (only Channel 7 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
// <i> Set DMA Channel priority
// </e>
#define RTE_USART2_TX_DMA 0
#define RTE_USART2_TX_DMA_NUMBER 1
#define RTE_USART2_TX_DMA_CHANNEL 7
#define RTE_USART2_TX_DMA_PRIORITY 0
// </e>
// <e> USART3 (Universal synchronous asynchronous receiver transmitter)
// <i> Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART
#define RTE_USART3 0
// <o> USART3_TX Pin <0=>Not Used <1=>PB10
#define RTE_USART3_TX_PORT_ID_DEF 0
#if (RTE_USART3_TX_PORT_ID_DEF == 0)
#define RTE_USART3_TX_DEF 0
#elif (RTE_USART3_TX_PORT_ID_DEF == 1)
#define RTE_USART3_TX_DEF 1
#define RTE_USART3_TX_PORT_DEF GPIOB
#define RTE_USART3_TX_BIT_DEF 10
#else
#error "Invalid USART3_TX Pin Configuration!"
#endif
// <o> USART3_RX Pin <0=>Not Used <1=>PB11
#define RTE_USART3_RX_PORT_ID_DEF 0
#if (RTE_USART3_RX_PORT_ID_DEF == 0)
#define RTE_USART3_RX_DEF 0
#elif (RTE_USART3_RX_PORT_ID_DEF == 1)
#define RTE_USART3_RX_DEF 1
#define RTE_USART3_RX_PORT_DEF GPIOB
#define RTE_USART3_RX_BIT_DEF 11
#else
#error "Invalid USART3_RX Pin Configuration!"
#endif
// <o> USART3_CK Pin <0=>Not Used <1=>PB12
#define RTE_USART3_CK_PORT_ID_DEF 0
#if (RTE_USART3_CK_PORT_ID_DEF == 0)
#define RTE_USART3_CK_DEF 0
#elif (RTE_USART3_CK_PORT_ID_DEF == 1)
#define RTE_USART3_CK_DEF 1
#define RTE_USART3_CK_PORT_DEF GPIOB
#define RTE_USART3_CK_BIT_DEF 12
#else
#error "Invalid USART3_CK Pin Configuration!"
#endif
// <o> USART3_CTS Pin <0=>Not Used <1=>PB13
#define RTE_USART3_CTS_PORT_ID_DEF 0
#if (RTE_USART3_CTS_PORT_ID_DEF == 0)
#define RTE_USART3_CTS_DEF 0
#elif (RTE_USART3_CTS_PORT_ID_DEF == 1)
#define RTE_USART3_CTS_DEF 1
#define RTE_USART3_CTS_PORT_DEF GPIOB
#define RTE_USART3_CTS_BIT_DEF 13
#else
#error "Invalid USART3_CTS Pin Configuration!"
#endif
// <o> USART3_RTS Pin <0=>Not Used <1=>PB14
#define RTE_USART3_RTS_PORT_ID_DEF 0
#if (RTE_USART3_RTS_PORT_ID_DEF == 0)
#define RTE_USART3_RTS_DEF 0
#elif (RTE_USART3_RTS_PORT_ID_DEF == 1)
#define RTE_USART3_RTS_DEF 1
#define RTE_USART3_RTS_PORT_DEF GPIOB
#define RTE_USART3_RTS_BIT_DEF 14
#else
#error "Invalid USART3_RTS Pin Configuration!"
#endif
// <e> USART3 Partial Pin Remap
// <i> Enable USART3 Partial Pin Remapping
#define RTE_USART3_REMAP_PARTIAL 0
// <o> USART3_TX Pin <0=>Not Used <1=>PC10
#define RTE_USART3_TX_PORT_ID_PARTIAL 0
#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0)
#define RTE_USART3_TX_PARTIAL 0
#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1)
#define RTE_USART3_TX_PARTIAL 1
#define RTE_USART3_TX_PORT_PARTIAL GPIOC
#define RTE_USART3_TX_BIT_PARTIAL 10
#else
#error "Invalid USART3_TX Pin Configuration!"
#endif
// <o> USART3_RX Pin <0=>Not Used <1=>PC11
#define RTE_USART3_RX_PORT_ID_PARTIAL 0
#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0)
#define RTE_USART3_RX_PARTIAL 0
#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1)
#define RTE_USART3_RX_PARTIAL 1
#define RTE_USART3_RX_PORT_PARTIAL GPIOC
#define RTE_USART3_RX_BIT_PARTIAL 11
#else
#error "Invalid USART3_RX Pin Configuration!"
#endif
// <o> USART3_CK Pin <0=>Not Used <1=>PC12
#define RTE_USART3_CK_PORT_ID_PARTIAL 0
#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0)
#define RTE_USART3_CK_PARTIAL 0
#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1)
#define RTE_USART3_CK_PARTIAL 1
#define RTE_USART3_CK_PORT_PARTIAL GPIOC
#define RTE_USART3_CK_BIT_PARTIAL 12
#else
#error "Invalid USART3_CK Pin Configuration!"
#endif
// </e>
// <e> USART3 Full Pin Remap
// <i> Enable USART3 Full Pin Remapping
#define RTE_USART3_REMAP_FULL 0
// <o> USART3_TX Pin <0=>Not Used <1=>PD8
#define RTE_USART3_TX_PORT_ID_FULL 0
#if (RTE_USART3_TX_PORT_ID_FULL == 0)
#define RTE_USART3_TX_FULL 0
#elif (RTE_USART3_TX_PORT_ID_FULL == 1)
#define RTE_USART3_TX_FULL 1
#define RTE_USART3_TX_PORT_FULL GPIOD
#define RTE_USART3_TX_BIT_FULL 8
#else
#error "Invalid USART3_TX Pin Configuration!"
#endif
// <o> USART3_RX Pin <0=>Not Used <1=>PD9
#define RTE_USART3_RX_PORT_ID_FULL 0
#if (RTE_USART3_RX_PORT_ID_FULL == 0)
#define RTE_USART3_RX_FULL 0
#elif (RTE_USART3_RX_PORT_ID_FULL == 1)
#define RTE_USART3_RX_FULL 1
#define RTE_USART3_RX_PORT_FULL GPIOD
#define RTE_USART3_RX_BIT_FULL 9
#else
#error "Invalid USART3_RX Pin Configuration!"
#endif
// <o> USART3_CK Pin <0=>Not Used <1=>PD10
#define RTE_USART3_CK_PORT_ID_FULL 0
#if (RTE_USART3_CK_PORT_ID_FULL == 0)
#define RTE_USART3_CK_FULL 0
#elif (RTE_USART3_CK_PORT_ID_FULL == 1)
#define RTE_USART3_CK_FULL 1
#define RTE_USART3_CK_PORT_FULL GPIOD
#define RTE_USART3_CK_BIT_FULL 10
#else
#error "Invalid USART3_CK Pin Configuration!"
#endif
// <o> USART3_CTS Pin <0=>Not Used <1=>PD11
#define RTE_USART3_CTS_PORT_ID_FULL 0
#if (RTE_USART3_CTS_PORT_ID_FULL == 0)
#define RTE_USART3_CTS_FULL 0
#elif (RTE_USART3_CTS_PORT_ID_FULL == 1)
#define RTE_USART3_CTS_FULL 1
#define RTE_USART3_CTS_PORT_FULL GPIOD
#define RTE_USART3_CTS_BIT_FULL 11
#else
#error "Invalid USART3_CTS Pin Configuration!"
#endif
// <o> USART3_RTS Pin <0=>Not Used <1=>PD12
#define RTE_USART3_RTS_PORT_ID_FULL 0
#if (RTE_USART3_RTS_PORT_ID_FULL == 0)
#define RTE_USART3_RTS_FULL 0
#elif (RTE_USART3_RTS_PORT_ID_FULL == 1)
#define RTE_USART3_RTS_FULL 1
#define RTE_USART3_RTS_PORT_FULL GPIOD
#define RTE_USART3_RTS_BIT_FULL 12
#else
#error "Invalid USART3_RTS Pin Configuration!"
#endif
// </e>
#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1))
#error "Invalid USART3 Pin Remap Configuration!"
#endif
#if (RTE_USART3_REMAP_FULL)
#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL
#define RTE_USART3_TX RTE_USART3_TX_FULL
#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL
#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL
#define RTE_USART3_RX RTE_USART3_RX_FULL
#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL
#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL
#define RTE_USART3_CK RTE_USART3_CK_FULL
#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL
#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL
#define RTE_USART3_CTS RTE_USART3_CTS_FULL
#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL
#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL
#define RTE_USART3_RTS RTE_USART3_RTS_FULL
#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL
#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL
#elif (RTE_USART3_REMAP_PARTIAL)
#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL
#define RTE_USART3_TX RTE_USART3_TX_PARTIAL
#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL
#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL
#define RTE_USART3_RX RTE_USART3_RX_PARTIAL
#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL
#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL
#define RTE_USART3_CK RTE_USART3_CK_PARTIAL
#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL
#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL
#define RTE_USART3_CTS RTE_USART3_CTS_DEF
#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF
#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF
#define RTE_USART3_RTS RTE_USART3_RTS_DEF
#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF
#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF
#else
#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP
#define RTE_USART3_TX RTE_USART3_TX_DEF
#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF
#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF
#define RTE_USART3_RX RTE_USART3_RX_DEF
#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF
#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF
#define RTE_USART3_CK RTE_USART3_CK_DEF
#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF
#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF
#define RTE_USART3_CTS RTE_USART3_CTS_DEF
#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF
#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF
#define RTE_USART3_RTS RTE_USART3_RTS_DEF
#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF
#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF
#endif
// <e> DMA Rx
// <o1> Number <1=>1
// <i> Selects DMA Number (only DMA1 can be used)
// <o2> Channel <3=>3
// <i> Selects DMA Channel (only Channel 3 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
// <i> Sets DMA Channel priority
// </e>
#define RTE_USART3_RX_DMA 0
#define RTE_USART3_RX_DMA_NUMBER 1
#define RTE_USART3_RX_DMA_CHANNEL 3
#define RTE_USART3_RX_DMA_PRIORITY 0
// <e> DMA Tx
// <o1> Number <1=>1
// <i> Selects DMA Number (only DMA1 can be used)
// <o2> Channel <2=>2
// <i> Selects DMA Channel (only Channel 2 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
// <i> Sets DMA Channel priority
// </e>
#define RTE_USART3_TX_DMA 0
#define RTE_USART3_TX_DMA_NUMBER 1
#define RTE_USART3_TX_DMA_CHANNEL 2
#define RTE_USART3_TX_DMA_PRIORITY 0
// </e>
// <e> UART4 (Universal asynchronous receiver transmitter)
// <i> Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART
#define RTE_UART4 0
#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP
// <o> UART4_TX Pin <0=>Not Used <1=>PC10
#define RTE_UART4_TX_ID 0
#if (RTE_UART4_TX_ID == 0)
#define RTE_UART4_TX 0
#elif (RTE_UART4_TX_ID == 1)
#define RTE_UART4_TX 1
#define RTE_UART4_TX_PORT GPIOC
#define RTE_UART4_TX_BIT 10
#else
#error "Invalid UART4_TX Pin Configuration!"
#endif
// <o> UART4_RX Pin <0=>Not Used <1=>PC11
#define RTE_UART4_RX_ID 0
#if (RTE_UART4_RX_ID == 0)
#define RTE_UART4_RX 0
#elif (RTE_UART4_RX_ID == 1)
#define RTE_UART4_RX 1
#define RTE_UART4_RX_PORT GPIOC
#define RTE_UART4_RX_BIT 11
#else
#error "Invalid UART4_RX Pin Configuration!"
#endif
// <e> DMA Rx
// <o1> Number <2=>2
// <i> Selects DMA Number (only DMA2 can be used)
// <o2> Channel <3=>3
// <i> Selects DMA Channel (only Channel 3 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
// <i> Sets DMA Channel priority
// </e>
#define RTE_UART4_RX_DMA 0
#define RTE_UART4_RX_DMA_NUMBER 2
#define RTE_UART4_RX_DMA_CHANNEL 3
#define RTE_UART4_RX_DMA_PRIORITY 0
// <e> DMA Tx
// <o1> Number <2=>2
// <i> Selects DMA Number (only DMA2 can be used)
// <o2> Channel <5=>5
// <i> Selects DMA Channel (only Channel 5 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
// <i> Sets DMA Channel priority
// </e>
#define RTE_UART4_TX_DMA 0
#define RTE_UART4_TX_DMA_NUMBER 2
#define RTE_UART4_TX_DMA_CHANNEL 5
#define RTE_UART4_TX_DMA_PRIORITY 0
// </e>
// <e> UART5 (Universal asynchronous receiver transmitter)
// <i> Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART
#define RTE_UART5 0
#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP
// <o> UART5_TX Pin <0=>Not Used <1=>PC12
#define RTE_UART5_TX_ID 0
#if (RTE_UART5_TX_ID == 0)
#define RTE_UART5_TX 0
#elif (RTE_UART5_TX_ID == 1)
#define RTE_UART5_TX 1
#define RTE_UART5_TX_PORT GPIOC
#define RTE_UART5_TX_BIT 12
#else
#error "Invalid UART5_TX Pin Configuration!"
#endif
// <o> UART5_RX Pin <0=>Not Used <1=>PD2
#define RTE_UART5_RX_ID 0
#if (RTE_UART5_RX_ID == 0)
#define RTE_UART5_RX 0
#elif (RTE_UART5_RX_ID == 1)
#define RTE_UART5_RX 1
#define RTE_UART5_RX_PORT GPIOD
#define RTE_UART5_RX_BIT 2
#else
#error "Invalid UART5_RX Pin Configuration!"
#endif
// </e>
// <e> I2C1 (Inter-integrated Circuit Interface 1)
// <i> Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C
#define RTE_I2C1 0
// <o> I2C1_SCL Pin <0=>PB6
#define RTE_I2C1_SCL_PORT_ID_DEF 0
#if (RTE_I2C1_SCL_PORT_ID_DEF == 0)
#define RTE_I2C1_SCL_PORT_DEF GPIOB
#define RTE_I2C1_SCL_BIT_DEF 6
#else
#error "Invalid I2C1_SCL Pin Configuration!"
#endif
// <o> I2C1_SDA Pin <0=>PB7
#define RTE_I2C1_SDA_PORT_ID_DEF 0
#if (RTE_I2C1_SDA_PORT_ID_DEF == 0)
#define RTE_I2C1_SDA_PORT_DEF GPIOB
#define RTE_I2C1_SDA_BIT_DEF 7
#else
#error "Invalid I2C1_SCL Pin Configuration!"
#endif
// <e> I2C1 Pin Remap
// <i> Enable I2C1 Pin Remapping
#define RTE_I2C1_REMAP_FULL 0
// <o> I2C1_SCL Pin <0=>PB8
#define RTE_I2C1_SCL_PORT_ID_FULL 0
#if (RTE_I2C1_SCL_PORT_ID_FULL == 0)
#define RTE_I2C1_SCL_PORT_FULL GPIOB
#define RTE_I2C1_SCL_BIT_FULL 8
#else
#error "Invalid I2C1_SCL Pin Configuration!"
#endif
// <o> I2C1_SDA Pin <0=>PB9
#define RTE_I2C1_SDA_PORT_ID_FULL 0
#if (RTE_I2C1_SDA_PORT_ID_FULL == 0)
#define RTE_I2C1_SDA_PORT_FULL GPIOB
#define RTE_I2C1_SDA_BIT_FULL 9
#else
#error "Invalid I2C1_SCL Pin Configuration!"
#endif
// </e>
#if (RTE_I2C1_REMAP_FULL)
#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP
#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL
#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL
#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL
#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL
#else
#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP
#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF
#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF
#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF
#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF
#endif
// <e> DMA Rx
// <o1> Number <1=>1
// <i> Selects DMA Number (only DMA1 can be used)
// <o2> Channel <7=>7
// <i> Selects DMA Channel (only Channel 7 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
// <i> Selects DMA Priority
// </e>
#define RTE_I2C1_RX_DMA 0
#define RTE_I2C1_RX_DMA_NUMBER 1
#define RTE_I2C1_RX_DMA_CHANNEL 7
#define RTE_I2C1_RX_DMA_PRIORITY 0
// <e> DMA Tx
// <o1> Number <1=>1
// <i> Selects DMA Number (only DMA1 can be used)
// <o2> Channel <6=>6
// <i> Selects DMA Channel (only Channel 6 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
// <i> Selects DMA Priority
// </e>
#define RTE_I2C1_TX_DMA 0
#define RTE_I2C1_TX_DMA_NUMBER 1
#define RTE_I2C1_TX_DMA_CHANNEL 6
#define RTE_I2C1_TX_DMA_PRIORITY 0
// </e>
// <e> I2C2 (Inter-integrated Circuit Interface 2)
// <i> Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C
#define RTE_I2C2 0
#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP
// <o> I2C2_SCL Pin <0=>PB10
#define RTE_I2C2_SCL_PORT_ID 0
#if (RTE_I2C2_SCL_PORT_ID == 0)
#define RTE_I2C2_SCL_PORT GPIOB
#define RTE_I2C2_SCL_BIT 10
#else
#error "Invalid I2C2_SCL Pin Configuration!"
#endif
// <o> I2C2_SDA Pin <0=>PB11
#define RTE_I2C2_SDA_PORT_ID 0
#if (RTE_I2C2_SDA_PORT_ID == 0)
#define RTE_I2C2_SDA_PORT GPIOB
#define RTE_I2C2_SDA_BIT 11
#else
#error "Invalid I2C2_SCL Pin Configuration!"
#endif
// <e> DMA Rx
// <o1> Number <1=>1
// <i> Selects DMA Number (only DMA1 can be used)
// <o2> Channel <5=>5
// <i> Selects DMA Channel (only Channel 5 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
// <i> Selects DMA Priority
// </e>
#define RTE_I2C2_RX_DMA 1
#define RTE_I2C2_RX_DMA_NUMBER 1
#define RTE_I2C2_RX_DMA_CHANNEL 5
#define RTE_I2C2_RX_DMA_PRIORITY 0
// <e> DMA Tx
// <o1> Number <1=>1
// <i> Selects DMA Number (only DMA1 can be used)
// <o2> Channel <4=>4
// <i> Selects DMA Channel (only Channel 4 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
// <i> Selects DMA Priority
// </e>
#define RTE_I2C2_TX_DMA 1
#define RTE_I2C2_TX_DMA_NUMBER 1
#define RTE_I2C2_TX_DMA_CHANNEL 4
#define RTE_I2C2_TX_DMA_PRIORITY 0
// </e>
// <e> SPI1 (Serial Peripheral Interface 1) [Driver_SPI1]
// <i> Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI
#define RTE_SPI1 0
// <e> SPI1_NSS Pin
// <i> Configure Pin if exists
// <i> GPIO Pxy (x = A..G, y = 0..15)
// <o1> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
// <4=>GPIOE <5=>GPIOF <6=>GPIOG
// <i> Selects Port Name
// <o2> Bit <0-15>
// <i> Selects Port Bit
// </e>
#define RTE_SPI1_NSS_PIN 1
#define RTE_SPI1_NSS_PORT GPIO_PORT(0)
#define RTE_SPI1_NSS_BIT 4
// <o> SPI1_SCK Pin <0=>PA5
#define RTE_SPI1_SCK_PORT_ID_DEF 0
#if (RTE_SPI1_SCK_PORT_ID_DEF == 0)
#define RTE_SPI1_SCK_PORT_DEF GPIOA
#define RTE_SPI1_SCK_BIT_DEF 5
#else
#error "Invalid SPI1_SCK Pin Configuration!"
#endif
// <o> SPI1_MISO Pin <0=>Not Used <1=>PA6
#define RTE_SPI1_MISO_PORT_ID_DEF 0
#if (RTE_SPI1_MISO_PORT_ID_DEF == 0)
#define RTE_SPI1_MISO_DEF 0
#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1)
#define RTE_SPI1_MISO_DEF 1
#define RTE_SPI1_MISO_PORT_DEF GPIOA
#define RTE_SPI1_MISO_BIT_DEF 6
#else
#error "Invalid SPI1_MISO Pin Configuration!"
#endif
// <o> SPI1_MOSI Pin <0=>Not Used <1=>PA7
#define RTE_SPI1_MOSI_PORT_ID_DEF 0
#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0)
#define RTE_SPI1_MOSI_DEF 0
#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1)
#define RTE_SPI1_MOSI_DEF 1
#define RTE_SPI1_MOSI_PORT_DEF GPIOA
#define RTE_SPI1_MOSI_BIT_DEF 7
#else
#error "Invalid SPI1_MISO Pin Configuration!"
#endif
// <e> SPI1 Pin Remap
// <i> Enable SPI1 Pin Remapping.
#define RTE_SPI1_REMAP 0
// <o> SPI1_SCK Pin <0=>PB3
#define RTE_SPI1_SCK_PORT_ID_FULL 0
#if (RTE_SPI1_SCK_PORT_ID_FULL == 0)
#define RTE_SPI1_SCK_PORT_FULL GPIOB
#define RTE_SPI1_SCK_BIT_FULL 3
#else
#error "Invalid SPI1_SCK Pin Configuration!"
#endif
// <o> SPI1_MISO Pin <0=>Not Used <1=>PB4
#define RTE_SPI1_MISO_PORT_ID_FULL 0
#if (RTE_SPI1_MISO_PORT_ID_FULL == 0)
#define RTE_SPI1_MISO_FULL 0
#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1)
#define RTE_SPI1_MISO_FULL 1
#define RTE_SPI1_MISO_PORT_FULL GPIOB
#define RTE_SPI1_MISO_BIT_FULL 4
#else
#error "Invalid SPI1_MISO Pin Configuration!"
#endif
// <o> SPI1_MOSI Pin <0=>Not Used <1=>PB5
#define RTE_SPI1_MOSI_PORT_ID_FULL 0
#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0)
#define RTE_SPI1_MOSI_FULL 0
#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1)
#define RTE_SPI1_MOSI_FULL 1
#define RTE_SPI1_MOSI_PORT_FULL GPIOB
#define RTE_SPI1_MOSI_BIT_FULL 5
#else
#error "Invalid SPI1_MOSI Pin Configuration!"
#endif
// </e>
#if (RTE_SPI1_REMAP)
#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP
#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL
#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL
#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL
#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL
#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL
#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL
#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL
#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL
#else
#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP
#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF
#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF
#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF
#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF
#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF
#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF
#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF
#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF
#endif
// <e> DMA Rx
// <o1> Number <1=>1
// <i> Selects DMA Number (only DMA1 can be used)
// <o2> Channel <2=>2
// <i> Selects DMA Channel (only Channel 2 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
// <i> Selects DMA Priority
// </e>
#define RTE_SPI1_RX_DMA 0
#define RTE_SPI1_RX_DMA_NUMBER 1
#define RTE_SPI1_RX_DMA_CHANNEL 2
#define RTE_SPI1_RX_DMA_PRIORITY 0
// <e> DMA Tx
// <o1> Number <1=>1
// <i> Selects DMA Number (only DMA1 can be used)
// <o2> Channel <3=>3
// <i> Selects DMA Channel (only Channel 3 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
// <i> Selects DMA Priority
// </e>
#define RTE_SPI1_TX_DMA 0
#define RTE_SPI1_TX_DMA_NUMBER 1
#define RTE_SPI1_TX_DMA_CHANNEL 3
#define RTE_SPI1_TX_DMA_PRIORITY 0
// </e>
// <e> SPI2 (Serial Peripheral Interface 2) [Driver_SPI2]
// <i> Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI
#define RTE_SPI2 0
// <e> SPI2_NSS Pin
// <i> Configure Pin if exists
// <i> GPIO Pxy (x = A..G, y = 0..15)
// <o1> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
// <4=>GPIOE <5=>GPIOF <6=>GPIOG
// <i> Selects Port Name
// <o2> Bit <0-15>
// <i> Selects Port Bit
// </e>
#define RTE_SPI2_NSS_PIN 1
#define RTE_SPI2_NSS_PORT GPIO_PORT(1)
#define RTE_SPI2_NSS_BIT 12
// <o> SPI2_SCK Pin <0=>PB13
#define RTE_SPI2_SCK_PORT_ID 0
#if (RTE_SPI2_SCK_PORT_ID == 0)
#define RTE_SPI2_SCK_PORT GPIOB
#define RTE_SPI2_SCK_BIT 13
#define RTE_SPI2_SCK_REMAP 0
#else
#error "Invalid SPI2_SCK Pin Configuration!"
#endif
// <o> SPI2_MISO Pin <0=>Not Used <1=>PB14
#define RTE_SPI2_MISO_PORT_ID 0
#if (RTE_SPI2_MISO_PORT_ID == 0)
#define RTE_SPI2_MISO 0
#elif (RTE_SPI2_MISO_PORT_ID == 1)
#define RTE_SPI2_MISO 1
#define RTE_SPI2_MISO_PORT GPIOB
#define RTE_SPI2_MISO_BIT 14
#define RTE_SPI2_MISO_REMAP 0
#else
#error "Invalid SPI2_MISO Pin Configuration!"
#endif
// <o> SPI2_MOSI Pin <0=>Not Used <1=>PB15
#define RTE_SPI2_MOSI_PORT_ID 0
#if (RTE_SPI2_MOSI_PORT_ID == 0)
#define RTE_SPI2_MOSI 0
#elif (RTE_SPI2_MOSI_PORT_ID == 1)
#define RTE_SPI2_MOSI 1
#define RTE_SPI2_MOSI_PORT GPIOB
#define RTE_SPI2_MOSI_BIT 15
#define RTE_SPI2_MOSI_REMAP 0
#else
#error "Invalid SPI2_MISO Pin Configuration!"
#endif
// <e> DMA Rx
// <o1> Number <1=>1
// <i> Selects DMA Number (only DMA1 can be used)
// <o2> Channel <4=>4
// <i> Selects DMA Channel (only Channel 4 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
// <i> Selects DMA Priority
// </e>
#define RTE_SPI2_RX_DMA 0
#define RTE_SPI2_RX_DMA_NUMBER 1
#define RTE_SPI2_RX_DMA_CHANNEL 4
#define RTE_SPI2_RX_DMA_PRIORITY 0
// <e> DMA Tx
// <o1> Number <1=>1
// <i> Selects DMA Number (only DMA1 can be used)
// <o2> Channel <5=>5
// <i> Selects DMA Channel (only Channel 5 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
// <i> Selects DMA Priority
// </e>
#define RTE_SPI2_TX_DMA 0
#define RTE_SPI2_TX_DMA_NUMBER 1
#define RTE_SPI2_TX_DMA_CHANNEL 5
#define RTE_SPI2_TX_DMA_PRIORITY 0
// </e>
// <e> SPI3 (Serial Peripheral Interface 3) [Driver_SPI3]
// <i> Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI
#define RTE_SPI3 0
// <e> SPI3_NSS Pin
// <i> Configure Pin if exists
// <i> GPIO Pxy (x = A..G, y = 0..15)
// <o1> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
// <4=>GPIOE <5=>GPIOF <6=>GPIOG
// <i> Selects Port Name
// <o2> Bit <0-15>
// <i> Selects Port Bit
// </e>
#define RTE_SPI3_NSS_PIN 1
#define RTE_SPI3_NSS_PORT GPIO_PORT(0)
#define RTE_SPI3_NSS_BIT 15
// <o> SPI3_SCK Pin <0=>PB3
#define RTE_SPI3_SCK_PORT_ID_DEF 0
#if (RTE_SPI3_SCK_PORT_ID_DEF == 0)
#define RTE_SPI3_SCK_PORT_DEF GPIOB
#define RTE_SPI3_SCK_BIT_DEF 3
#else
#error "Invalid SPI3_SCK Pin Configuration!"
#endif
// <o> SPI3_MISO Pin <0=>Not Used <1=>PB4
#define RTE_SPI3_MISO_PORT_ID_DEF 0
#if (RTE_SPI3_MISO_PORT_ID_DEF == 0)
#define RTE_SPI3_MISO_DEF 0
#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1)
#define RTE_SPI3_MISO_DEF 1
#define RTE_SPI3_MISO_PORT_DEF GPIOB
#define RTE_SPI3_MISO_BIT_DEF 4
#else
#error "Invalid SPI3_MISO Pin Configuration!"
#endif
// <o> SPI3_MOSI <0=>Not Used Pin <1=>PB5
#define RTE_SPI3_MOSI_PORT_ID_DEF 0
#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0)
#define RTE_SPI3_MOSI_DEF 0
#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1)
#define RTE_SPI3_MOSI_DEF 1
#define RTE_SPI3_MOSI_PORT_DEF GPIOB
#define RTE_SPI3_MOSI_BIT_DEF 5
#else
#error "Invalid SPI3_MOSI Pin Configuration!"
#endif
// <e> SPI3 Pin Remap
// <i> Enable SPI3 Pin Remapping.
// <i> SPI 3 Pin Remapping is available only in connectivity line devices!
#define RTE_SPI3_REMAP 0
// <o> SPI3_SCK Pin <0=>PC10
#define RTE_SPI3_SCK_PORT_ID_FULL 0
#if (RTE_SPI3_SCK_PORT_ID_FULL == 0)
#define RTE_SPI3_SCK_PORT_FULL GPIOC
#define RTE_SPI3_SCK_BIT_FULL 10
#else
#error "Invalid SPI3_SCK Pin Configuration!"
#endif
// <o> SPI3_MISO Pin <0=>Not Used <1=>PC11
#define RTE_SPI3_MISO_PORT_ID_FULL 0
#if (RTE_SPI3_MISO_PORT_ID_FULL == 0)
#define RTE_SPI3_MISO_FULL 0
#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1)
#define RTE_SPI3_MISO_FULL 1
#define RTE_SPI3_MISO_PORT_FULL GPIOC
#define RTE_SPI3_MISO_BIT_FULL 11
#else
#error "Invalid SPI3_MISO Pin Configuration!"
#endif
// <o> SPI3_MOSI Pin <0=>Not Used <1=>PC12
#define RTE_SPI3_MOSI_PORT_ID_FULL 0
#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0)
#define RTE_SPI3_MOSI_FULL 0
#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1)
#define RTE_SPI3_MOSI_FULL 1
#define RTE_SPI3_MOSI_PORT_FULL GPIOC
#define RTE_SPI3_MOSI_BIT_FULL 12
#else
#error "Invalid SPI3_MOSI Pin Configuration!"
#endif
// </e>
#if (RTE_SPI3_REMAP)
#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP
#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL
#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL
#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL
#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL
#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL
#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL
#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL
#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL
#else
#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP
#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF
#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF
#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF
#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF
#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF
#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF
#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF
#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF
#endif
// <e> DMA Rx
// <o1> Number <2=>2
// <i> Selects DMA Number (only DMA2 can be used)
// <o2> Channel <1=>1
// <i> Selects DMA Channel (only Channel 1 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
// <i> Selects DMA Priority
// </e>
#define RTE_SPI3_RX_DMA 0
#define RTE_SPI3_RX_DMA_NUMBER 2
#define RTE_SPI3_RX_DMA_CHANNEL 1
#define RTE_SPI3_RX_DMA_PRIORITY 0
// <e> DMA Tx
// <o1> Number <2=>2
// <i> Selects DMA Number (only DMA2 can be used)
// <o2> Channel <2=>2
// <i> Selects DMA Channel (only Channel 2 can be used)
// <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
// <i> Selects DMA Priority
// </e>
#define RTE_SPI3_TX_DMA 0
#define RTE_SPI3_TX_DMA_NUMBER 2
#define RTE_SPI3_TX_DMA_CHANNEL 2
#define RTE_SPI3_TX_DMA_PRIORITY 0
// </e>
// <e> SDIO (Secure Digital Input/Output) [Driver_MCI0]
// <i> Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI
#define RTE_SDIO 0
// <h> SDIO Peripheral Bus
// <o> SDIO_CK Pin <0=>PC12
#define RTE_SDIO_CK_PORT_ID 0
#if (RTE_SDIO_CK_PORT_ID == 0)
#define RTE_SDIO_CK_PORT GPIOC
#define RTE_SDIO_CK_PIN 12
#else
#error "Invalid SDIO_CLK Pin Configuration!"
#endif
// <o> SDIO_CMD Pin <0=>PD2
#define RTE_SDIO_CMD_PORT_ID 0
#if (RTE_SDIO_CMD_PORT_ID == 0)
#define RTE_SDIO_CMD_PORT GPIOD
#define RTE_SDIO_CMD_PIN 2
#else
#error "Invalid SDIO_CMD Pin Configuration!"
#endif
// <o> SDIO_D0 Pin <0=>PC8
#define RTE_SDIO_D0_PORT_ID 0
#if (RTE_SDIO_D0_PORT_ID == 0)
#define RTE_SDIO_D0_PORT GPIOC
#define RTE_SDIO_D0_PIN 8
#else
#error "Invalid SDIO_DAT0 Pin Configuration!"
#endif
// <e> SDIO_D[1 .. 3]
#define RTE_SDIO_BUS_WIDTH_4 1
// <o> SDIO_D1 Pin <0=>PC9
#define RTE_SDIO_D1_PORT_ID 0
#if (RTE_SDIO_D1_PORT_ID == 0)
#define RTE_SDIO_D1_PORT GPIOC
#define RTE_SDIO_D1_PIN 9
#else
#error "Invalid SDIO_D1 Pin Configuration!"
#endif
// <o> SDIO_D2 Pin <0=>PC10
#define RTE_SDIO_D2_PORT_ID 0
#if (RTE_SDIO_D2_PORT_ID == 0)
#define RTE_SDIO_D2_PORT GPIOC
#define RTE_SDIO_D2_PIN 10
#else
#error "Invalid SDIO_D2 Pin Configuration!"
#endif
// <o> SDIO_D3 Pin <0=>PC11
#define RTE_SDIO_D3_PORT_ID 0
#if (RTE_SDIO_D3_PORT_ID == 0)
#define RTE_SDIO_D3_PORT GPIOC
#define RTE_SDIO_D3_PIN 11
#else
#error "Invalid SDIO_D3 Pin Configuration!"
#endif
// </e> SDIO_D[1 .. 3]
// <e> SDIO_D[4 .. 7]
#define RTE_SDIO_BUS_WIDTH_8 0
// <o> SDIO_D4 Pin <0=>PB8
#define RTE_SDIO_D4_PORT_ID 0
#if (RTE_SDIO_D4_PORT_ID == 0)
#define RTE_SDIO_D4_PORT GPIOB
#define RTE_SDIO_D4_PIN 8
#else
#error "Invalid SDIO_D4 Pin Configuration!"
#endif
// <o> SDIO_D5 Pin <0=>PB9
#define RTE_SDIO_D5_PORT_ID 0
#if (RTE_SDIO_D5_PORT_ID == 0)
#define RTE_SDIO_D5_PORT GPIOB
#define RTE_SDIO_D5_PIN 9
#else
#error "Invalid SDIO_D5 Pin Configuration!"
#endif
// <o> SDIO_D6 Pin <0=>PC6
#define RTE_SDIO_D6_PORT_ID 0
#if (RTE_SDIO_D6_PORT_ID == 0)
#define RTE_SDIO_D6_PORT GPIOC
#define RTE_SDIO_D6_PIN 6
#else
#error "Invalid SDIO_D6 Pin Configuration!"
#endif
// <o> SDIO_D7 Pin <0=>PC7
#define RTE_SDIO_D7_PORT_ID 0
#if (RTE_SDIO_D7_PORT_ID == 0)
#define RTE_SDIO_D7_PORT GPIOC
#define RTE_SDIO_D7_PIN 7
#else
#error "Invalid SDIO_D7 Pin Configuration!"
#endif
// </e> SDIO_D[4 .. 7]
// </h> SDIO Peripheral Bus
// <e> Card Detect Pin
// <i> Configure Pin if exists
// <i> GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
// <o1> Active State <0=>Low <1=>High
// <i> Selects Active State Logical Level
// <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
// <4=>GPIOE <5=>GPIOF <6=>GPIOG
// <i> Selects Port Name
// <o3> Bit <0-15>
// <i> Selects Port Bit
// </e>
#define RTE_SDIO_CD_EN 1
#define RTE_SDIO_CD_ACTIVE 0
#define RTE_SDIO_CD_PORT GPIO_PORT(5)
#define RTE_SDIO_CD_PIN 11
// <e> Write Protect Pin
// <i> Configure Pin if exists
// <i> GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
// <o1> Active State <0=>Low <1=>High
// <i> Selects Active State Logical Level
// <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
// <4=>GPIOE <5=>GPIOF <6=>GPIOG
// <i> Selects Port Name
// <o3> Bit <0-15>
// <i> Selects Port Bit
// </e>
#define RTE_SDIO_WP_EN 0
#define RTE_SDIO_WP_ACTIVE 1
#define RTE_SDIO_WP_PORT GPIO_PORT(0)
#define RTE_SDIO_WP_PIN 10
// <h> DMA
// <o0> Number <2=>2
// <i> Selects DMA Number (only DMA2 can be used)
// <o1> Channel <4=>4
// <i> Selects DMA Channel (only Channel 4 can be used)
// <o2> Priority <0=>Low <1=>Medium <2=>High <3=>Very High
// <i> Selects DMA Priority
// </h>
#define RTE_SDIO_DMA_NUMBER 2
#define RTE_SDIO_DMA_CHANNEL 4
#define RTE_SDIO_DMA_PRIORITY 0
// </e>
// <e> CAN1 (Controller Area Network 1) [Driver_CAN1]
// <i> Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN
#define RTE_CAN1 0
// <o> CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0
#define RTE_CAN1_RX_PORT_ID 0
#if (RTE_CAN1_RX_PORT_ID == 0)
#define RTE_CAN1_RX_PORT GPIOA
#define RTE_CAN1_RX_BIT 11
#elif (RTE_CAN1_RX_PORT_ID == 1)
#define RTE_CAN1_RX_PORT GPIOB
#define RTE_CAN1_RX_BIT 8
#elif (RTE_CAN1_RX_PORT_ID == 2)
#define RTE_CAN1_RX_PORT GPIOD
#define RTE_CAN1_RX_BIT 0
#else
#error "Invalid CAN1_RX Pin Configuration!"
#endif
// <o> CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1
#define RTE_CAN1_TX_PORT_ID 0
#if (RTE_CAN1_TX_PORT_ID == 0)
#define RTE_CAN1_TX_PORT GPIOA
#define RTE_CAN1_TX_BIT 12
#elif (RTE_CAN1_TX_PORT_ID == 1)
#define RTE_CAN1_TX_PORT GPIOB
#define RTE_CAN1_TX_BIT 9
#elif (RTE_CAN1_TX_PORT_ID == 2)
#define RTE_CAN1_TX_PORT GPIOD
#define RTE_CAN1_TX_BIT 1
#else
#error "Invalid CAN1_TX Pin Configuration!"
#endif
// </e>
// <e> CAN2 (Controller Area Network 2) [Driver_CAN2]
// <i> Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN
#define RTE_CAN2 0
// <o> CAN2_RX Pin <0=>PB5 <1=>PB12
#define RTE_CAN2_RX_PORT_ID 0
#if (RTE_CAN2_RX_PORT_ID == 0)
#define RTE_CAN2_RX_PORT GPIOB
#define RTE_CAN2_RX_BIT 5
#elif (RTE_CAN2_RX_PORT_ID == 1)
#define RTE_CAN2_RX_PORT GPIOB
#define RTE_CAN2_RX_BIT 12
#else
#error "Invalid CAN2_RX Pin Configuration!"
#endif
// <o> CAN2_TX Pin <0=>PB6 <1=>PB13
#define RTE_CAN2_TX_PORT_ID 0
#if (RTE_CAN2_TX_PORT_ID == 0)
#define RTE_CAN2_TX_PORT GPIOB
#define RTE_CAN2_TX_BIT 6
#elif (RTE_CAN2_TX_PORT_ID == 1)
#define RTE_CAN2_TX_PORT GPIOB
#define RTE_CAN2_TX_BIT 13
#else
#error "Invalid CAN2_TX Pin Configuration!"
#endif
// </e>
// <e> ETH (Ethernet Interface) [Driver_ETH_MAC0]
// <i> Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC
#define RTE_ETH 0
// <e> MII (Media Independent Interface)
// <i> Enable Media Independent Interface pin configuration
#define RTE_ETH_MII 0
// <o> ETH_MII_TX_CLK Pin <0=>PC3
#define RTE_ETH_MII_TX_CLK_PORT_ID 0
#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0)
#define RTE_ETH_MII_TX_CLK_PORT GPIOC
#define RTE_ETH_MII_TX_CLK_PIN 3
#else
#error "Invalid ETH_MII_TX_CLK Pin Configuration!"
#endif
// <o> ETH_MII_TXD0 Pin <0=>PB12
#define RTE_ETH_MII_TXD0_PORT_ID 0
#if (RTE_ETH_MII_TXD0_PORT_ID == 0)
#define RTE_ETH_MII_TXD0_PORT GPIOB
#define RTE_ETH_MII_TXD0_PIN 12
#else
#error "Invalid ETH_MII_TXD0 Pin Configuration!"
#endif
// <o> ETH_MII_TXD1 Pin <0=>PB13
#define RTE_ETH_MII_TXD1_PORT_ID 0
#if (RTE_ETH_MII_TXD1_PORT_ID == 0)
#define RTE_ETH_MII_TXD1_PORT GPIOB
#define RTE_ETH_MII_TXD1_PIN 13
#else
#error "Invalid ETH_MII_TXD1 Pin Configuration!"
#endif
// <o> ETH_MII_TXD2 Pin <0=>PC2
#define RTE_ETH_MII_TXD2_PORT_ID 0
#if (RTE_ETH_MII_TXD2_PORT_ID == 0)
#define RTE_ETH_MII_TXD2_PORT GPIOC
#define RTE_ETH_MII_TXD2_PIN 2
#else
#error "Invalid ETH_MII_TXD2 Pin Configuration!"
#endif
// <o> ETH_MII_TXD3 Pin <0=>PB8
#define RTE_ETH_MII_TXD3_PORT_ID 0
#if (RTE_ETH_MII_TXD3_PORT_ID == 0)
#define RTE_ETH_MII_TXD3_PORT GPIOB
#define RTE_ETH_MII_TXD3_PIN 8
#else
#error "Invalid ETH_MII_TXD3 Pin Configuration!"
#endif
// <o> ETH_MII_TX_EN Pin <0=>PB11
#define RTE_ETH_MII_TX_EN_PORT_ID 0
#if (RTE_ETH_MII_TX_EN_PORT_ID == 0)
#define RTE_ETH_MII_TX_EN_PORT GPIOB
#define RTE_ETH_MII_TX_EN_PIN 11
#else
#error "Invalid ETH_MII_TX_EN Pin Configuration!"
#endif
// <o> ETH_MII_RX_CLK Pin <0=>PA1
#define RTE_ETH_MII_RX_CLK_PORT_ID 0
#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0)
#define RTE_ETH_MII_RX_CLK_PORT GPIOA
#define RTE_ETH_MII_RX_CLK_PIN 1
#else
#error "Invalid ETH_MII_RX_CLK Pin Configuration!"
#endif
// <o> ETH_MII_RXD0 Pin <0=>PC4
#define RTE_ETH_MII_RXD0_DEF 0
// <o> ETH_MII_RXD1 Pin <0=>PC5
#define RTE_ETH_MII_RXD1_DEF 0
// <o> ETH_MII_RXD2 Pin <0=>PB0
#define RTE_ETH_MII_RXD2_DEF 0
// <o> ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12
#define RTE_ETH_MII_RXD3_DEF 0
// <o> ETH_MII_RX_DV Pin <0=>PA7
#define RTE_ETH_MII_RX_DV_DEF 0
// <o> ETH_MII_RX_ER Pin <0=>PB10
#define RTE_ETH_MII_RX_ER_PORT_ID 0
#if (RTE_ETH_MII_RX_ER_PORT_ID == 0)
#define RTE_ETH_MII_RX_ER_PORT GPIOB
#define RTE_ETH_MII_RX_ER_PIN 10
#else
#error "Invalid ETH_MII_RX_ER Pin Configuration!"
#endif
// <o> ETH_MII_CRS Pin <0=>PA0
#define RTE_ETH_MII_CRS_PORT_ID 0
#if (RTE_ETH_MII_CRS_PORT_ID == 0)
#define RTE_ETH_MII_CRS_PORT GPIOA
#define RTE_ETH_MII_CRS_PIN 0
#else
#error "Invalid ETH_MII_CRS Pin Configuration!"
#endif
// <o> ETH_MII_COL Pin <0=>PA3
#define RTE_ETH_MII_COL_PORT_ID 0
#if (RTE_ETH_MII_COL_PORT_ID == 0)
#define RTE_ETH_MII_COL_PORT GPIOA
#define RTE_ETH_MII_COL_PIN 3
#else
#error "Invalid ETH_MII_COL Pin Configuration!"
#endif
// <e> Ethernet MAC I/O remapping
// <i> Remap Ethernet pins
#define RTE_ETH_MII_REMAP 0
// <o> ETH_MII_RXD0 Pin <1=>PD9
#define RTE_ETH_MII_RXD0_REMAP 1
// <o> ETH_MII_RXD1 Pin <1=>PD10
#define RTE_ETH_MII_RXD1_REMAP 1
// <o> ETH_MII_RXD2 Pin <1=>PD11
#define RTE_ETH_MII_RXD2_REMAP 1
// <o> ETH_MII_RXD3 Pin <1=>PD12
#define RTE_ETH_MII_RXD3_REMAP 1
// <o> ETH_MII_RX_DV Pin <1=>PD8
#define RTE_ETH_MII_RX_DV_REMAP 1
// </e>
// </e>
#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0))
#define RTE_ETH_MII_RXD0_PORT GPIOC
#define RTE_ETH_MII_RXD0_PIN 4
#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1))
#define RTE_ETH_MII_RXD0_PORT GPIOD
#define RTE_ETH_MII_RXD0_PIN 9
#else
#error "Invalid ETH_MII_RXD0 Pin Configuration!"
#endif
#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0))
#define RTE_ETH_MII_RXD1_PORT GPIOC
#define RTE_ETH_MII_RXD1_PIN 5
#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1))
#define RTE_ETH_MII_RXD1_PORT GPIOD
#define RTE_ETH_MII_RXD1_PIN 10
#else
#error "Invalid ETH_MII_RXD1 Pin Configuration!"
#endif
#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0))
#define RTE_ETH_MII_RXD2_PORT GPIOB
#define RTE_ETH_MII_RXD2_PIN 0
#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1))
#define RTE_ETH_MII_RXD2_PORT GPIOD
#define RTE_ETH_MII_RXD2_PIN 11
#else
#error "Invalid ETH_MII_RXD2 Pin Configuration!"
#endif
#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0))
#define RTE_ETH_MII_RXD3_PORT GPIOB
#define RTE_ETH_MII_RXD3_PIN 1
#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1))
#define RTE_ETH_MII_RXD3_PORT GPIOD
#define RTE_ETH_MII_RXD3_PIN 12
#else
#error "Invalid ETH_MII_RXD3 Pin Configuration!"
#endif
#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0))
#define RTE_ETH_MII_RX_DV_PORT GPIOA
#define RTE_ETH_MII_RX_DV_PIN 7
#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1))
#define RTE_ETH_MII_RX_DV_PORT GPIOD
#define RTE_ETH_MII_RX_DV_PIN 8
#else
#error "Invalid ETH_MII_RX_DV Pin Configuration!"
#endif
// <e> RMII (Reduced Media Independent Interface)
#define RTE_ETH_RMII 0
// <o> ETH_RMII_TXD0 Pin <0=>PB12
#define RTE_ETH_RMII_TXD0_PORT_ID 0
#if (RTE_ETH_RMII_TXD0_PORT_ID == 0)
#define RTE_ETH_RMII_TXD0_PORT GPIOB
#define RTE_ETH_RMII_TXD0_PIN 12
#else
#error "Invalid ETH_RMII_TXD0 Pin Configuration!"
#endif
// <o> ETH_RMII_TXD1 Pin <0=>PB13
#define RTE_ETH_RMII_TXD1_PORT_ID 0
#if (RTE_ETH_RMII_TXD1_PORT_ID == 0)
#define RTE_ETH_RMII_TXD1_PORT GPIOB
#define RTE_ETH_RMII_TXD1_PIN 13
#else
#error "Invalid ETH_RMII_TXD1 Pin Configuration!"
#endif
// <o> ETH_RMII_TX_EN Pin <0=>PB11
#define RTE_ETH_RMII_TX_EN_PORT_ID 0
#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0)
#define RTE_ETH_RMII_TX_EN_PORT GPIOB
#define RTE_ETH_RMII_TX_EN_PIN 11
#else
#error "Invalid ETH_RMII_TX_EN Pin Configuration!"
#endif
// <o> ETH_RMII_RXD0 Pin <0=>PC4
#define RTE_ETH_RMII_RXD0_DEF 0
// <o> ETH_RMII_RXD1 Pin <0=>PC5
#define RTE_ETH_RMII_RXD1_DEF 0
// <o> ETH_RMII_REF_CLK Pin <0=>PA1
#define RTE_ETH_RMII_REF_CLK_PORT_ID 0
#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0)
#define RTE_ETH_RMII_REF_CLK_PORT GPIOA
#define RTE_ETH_RMII_REF_CLK_PIN 1
#else
#error "Invalid ETH_RMII_REF_CLK Pin Configuration!"
#endif
// <o> ETH_RMII_CRS_DV Pin <0=>PA7
#define RTE_ETH_RMII_CRS_DV_DEF 0
// <e> Ethernet MAC I/O remapping
// <i> Remap Ethernet pins
#define RTE_ETH_RMII_REMAP 0
// <o> ETH_RMII_RXD0 Pin <1=>PD9
#define RTE_ETH_RMII_RXD0_REMAP 1
// <o> ETH_RMII_RXD1 Pin <1=>PD10
#define RTE_ETH_RMII_RXD1_REMAP 1
// <o> ETH_RMII_CRS_DV Pin <1=>PD8
#define RTE_ETH_RMII_CRS_DV_REMAP 1
// </e>
#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0))
#define RTE_ETH_RMII_RXD0_PORT GPIOC
#define RTE_ETH_RMII_RXD0_PIN 4
#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1))
#define RTE_ETH_RMII_RXD0_PORT GPIOD
#define RTE_ETH_RMII_RXD0_PIN 9
#else
#error "Invalid ETH_RMII_RXD0 Pin Configuration!"
#endif
#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0))
#define RTE_ETH_RMII_RXD1_PORT GPIOC
#define RTE_ETH_RMII_RXD1_PIN 5
#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1))
#define RTE_ETH_RMII_RXD1_PORT GPIOD
#define RTE_ETH_RMII_RXD1_PIN 10
#else
#error "Invalid ETH_RMII_RXD1 Pin Configuration!"
#endif
#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0))
#define RTE_ETH_RMII_CRS_DV_PORT GPIOA
#define RTE_ETH_RMII_CRS_DV_PIN 7
#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1))
#define RTE_ETH_RMII_CRS_DV_PORT GPIOD
#define RTE_ETH_RMII_CRS_DV_PIN 8
#else
#error "Invalid ETH_RMII_CRS_DV Pin Configuration!"
#endif
// </e>
// <h> Management Data Interface
// <o> ETH_MDC Pin <0=>PC1
#define RTE_ETH_MDI_MDC_PORT_ID 0
#if (RTE_ETH_MDI_MDC_PORT_ID == 0)
#define RTE_ETH_MDI_MDC_PORT GPIOC
#define RTE_ETH_MDI_MDC_PIN 1
#else
#error "Invalid ETH_MDC Pin Configuration!"
#endif
// <o> ETH_MDIO Pin <0=>PA2
#define RTE_ETH_MDI_MDIO_PORT_ID 0
#if (RTE_ETH_MDI_MDIO_PORT_ID == 0)
#define RTE_ETH_MDI_MDIO_PORT GPIOA
#define RTE_ETH_MDI_MDIO_PIN 2
#else
#error "Invalid ETH_MDIO Pin Configuration!"
#endif
// </h>
// <o> Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled
#define RTE_ETH_REF_CLOCK_ID 0
#if (RTE_ETH_REF_CLOCK_ID == 0)
#define RTE_ETH_REF_CLOCK 0
#elif (RTE_ETH_REF_CLOCK_ID == 1)
#define RTE_ETH_REF_CLOCK 1
#else
#error "Invalid MCO Ethernet Reference Clock Configuration!"
#endif
// </e>
// <e> USB Device Full-speed
// <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
#define RTE_USB_DEVICE 0
// <e> CON On/Off Pin
// <i> Configure Pin for driving D+ pull-up
// <i> GPIO Pxy (x = A..G, y = 0..15)
// <o1> Active State <0=>Low <1=>High
// <i> Selects Active State Logical Level
// <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
// <4=>GPIOE <5=>GPIOF <6=>GPIOG
// <i> Selects Port Name
// <o3> Bit <0-15>
// <i> Selects Port Bit
// </e>
#define RTE_USB_DEVICE_CON_PIN 1
#define RTE_USB_DEVICE_CON_ACTIVE 0
#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1)
#define RTE_USB_DEVICE_CON_BIT 14
// </e>
// <e> USB OTG Full-speed
#define RTE_USB_OTG_FS 0
// <e> Host [Driver_USBH0]
// <i> Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
#define RTE_USB_OTG_FS_HOST 0
// <e> VBUS Power On/Off Pin
// <i> Configure Pin for driving VBUS
// <i> GPIO Pxy (x = A..G, y = 0..15)
// <o1> Active State <0=>Low <1=>High
// <i> Selects Active State Logical Level
// <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
// <4=>GPIOE <5=>GPIOF <6=>GPIOG
// <i> Selects Port Name
// <o3> Bit <0-15>
// <i> Selects Port Bit
// </e>
#define RTE_OTG_FS_VBUS_PIN 1
#define RTE_OTG_FS_VBUS_ACTIVE 0
#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2)
#define RTE_OTG_FS_VBUS_BIT 9
// <e> Overcurrent Detection Pin
// <i> Configure Pin for overcurrent detection
// <i> GPIO Pxy (x = A..G, y = 0..15)
// <o1> Active State <0=>Low <1=>High
// <i> Selects Active State Logical Level
// <o2> Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
// <4=>GPIOE <5=>GPIOF <6=>GPIOG
// <i> Selects Port Name
// <o3> Bit <0-15>
// <i> Selects Port Bit
// </e>
#define RTE_OTG_FS_OC_PIN 1
#define RTE_OTG_FS_OC_ACTIVE 0
#define RTE_OTG_FS_OC_PORT GPIO_PORT(4)
#define RTE_OTG_FS_OC_BIT 1
// </e>
// </e>
#endif /* __RTE_DEVICE_H */
RTE/Device/STM32F103ZE/startup_stm32f10x_hd.s 0 → 100644
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.1
;* Date : 08-September-2021
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Copyright (c) 2011 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
RTE/Device/STM32F103ZE/system_stm32f10x.c 0 → 100644
/**
******************************************************************************
* @file system_stm32f10x.c
* @author MCD Application Team
* @version V3.5.1
* @date 08-September-2021
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* factors, AHB/APBx prescalers and Flash settings).
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f10x_xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
* the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
* When HSE is used as system clock source, directly or through PLL, and you
* are using different crystal you have to adapt the HSE value to your own
* configuration.
*
******************************************************************************
* @attention
*
* Copyright (c) 2011 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f10x_system
* @{
*/
/** @addtogroup STM32F10x_System_Private_Includes
* @{
*/
#include "stm32f10x.h"
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_Defines
* @{
*/
/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
frequency (after reset the HSI is used as SYSCLK source)
IMPORTANT NOTE:
==============
1. After each device reset the HSI is used as System clock source.
2. Please make sure that the selected System clock doesn't exceed your device's
maximum frequency.
3. If none of the define below is enabled, the HSI is used as System clock
source.
4. The System clock configuration functions provided within this file assume that:
- For Low, Medium and High density Value line devices an external 8MHz
crystal is used to drive the System clock.
- For Low, Medium and High density devices an external 8MHz crystal is
used to drive the System clock.
- For Connectivity line devices an external 25MHz crystal is used to drive
the System clock.
If you are using different crystal you have to adapt those functions accordingly.
*/
#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
/* #define SYSCLK_FREQ_HSE HSE_VALUE */
#define SYSCLK_FREQ_24MHz 24000000
#else
/* #define SYSCLK_FREQ_HSE HSE_VALUE */
/* #define SYSCLK_FREQ_24MHz 24000000 */
/* #define SYSCLK_FREQ_36MHz 36000000 */
/* #define SYSCLK_FREQ_48MHz 48000000 */
/* #define SYSCLK_FREQ_56MHz 56000000 */
#define SYSCLK_FREQ_72MHz 72000000
#endif
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
/* #define DATA_IN_ExtSRAM */
#endif
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_Variables
* @{
*/
/*******************************************************************************
* Clock Definitions
*******************************************************************************/
#ifdef SYSCLK_FREQ_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_24MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_36MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_48MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_56MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_72MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
#else /*!< HSI Selected as System Clock source */
uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
#endif
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
* @{
*/
static void SetSysClock(void);
#ifdef SYSCLK_FREQ_HSE
static void SetSysClockToHSE(void);
#elif defined SYSCLK_FREQ_24MHz
static void SetSysClockTo24(void);
#elif defined SYSCLK_FREQ_36MHz
static void SetSysClockTo36(void);
#elif defined SYSCLK_FREQ_48MHz
static void SetSysClockTo48(void);
#elif defined SYSCLK_FREQ_56MHz
static void SetSysClockTo56(void);
#elif defined SYSCLK_FREQ_72MHz
static void SetSysClockTo72(void);
#endif
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemCoreClock variable.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#ifndef STM32F10X_CL
RCC->CFGR &= (uint32_t)0xF8FF0000;
#else
RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif /* STM32F10X_CL */
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;
#ifdef STM32F10X_CL
/* Reset PLL2ON and PLL3ON bits */
RCC->CR &= (uint32_t)0xEBFFFFFF;
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x00FF0000;
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#else
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
#endif /* STM32F10X_CL */
#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
#endif
/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
/* Configure the Flash Latency cycles and enable prefetch buffer */
SetSysClock();
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
* 8 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
* 8 MHz or 25 MHz, depending on the product used), user has to ensure
* that HSE_VALUE is same as the real frequency of the crystal used.
* Otherwise, this function may have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmull = 0, pllsource = 0;
#ifdef STM32F10X_CL
uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
#endif /* STM32F10X_CL */
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
uint32_t prediv1factor = 0;
#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
#ifndef STM32F10X_CL
pllmull = ( pllmull >> 18) + 2;
if (pllsource == 0x00)
{
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
}
else
{
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
#else
/* HSE selected as PLL clock entry */
if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
{/* HSE oscillator clock divided by 2 */
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
}
else
{
SystemCoreClock = HSE_VALUE * pllmull;
}
#endif
}
#else
pllmull = pllmull >> 18;
if (pllmull != 0x0D)
{
pllmull += 2;
}
else
{ /* PLL multiplication factor = PLL input clock * 6.5 */
pllmull = 13 / 2;
}
if (pllsource == 0x00)
{
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
}
else
{/* PREDIV1 selected as PLL clock entry */
/* Get PREDIV1 clock source and division factor */
prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
if (prediv1source == 0)
{
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
}
else
{/* PLL2 clock selected as PREDIV1 clock entry */
/* Get PREDIV2 division factor and PLL2 multiplication factor */
prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
}
}
#endif /* STM32F10X_CL */
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
* @param None
* @retval None
*/
static void SetSysClock(void)
{
#ifdef SYSCLK_FREQ_HSE
SetSysClockToHSE();
#elif defined SYSCLK_FREQ_24MHz
SetSysClockTo24();
#elif defined SYSCLK_FREQ_36MHz
SetSysClockTo36();
#elif defined SYSCLK_FREQ_48MHz
SetSysClockTo48();
#elif defined SYSCLK_FREQ_56MHz
SetSysClockTo56();
#elif defined SYSCLK_FREQ_72MHz
SetSysClockTo72();
#endif
/* If none of the define above is enabled, the HSI is used as System clock
source (default after reset) */
}
/**
* @brief Setup the external memory controller. Called in startup_stm32f10x.s
* before jump to __main
* @param None
* @retval None
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f10x_xx.s/.c before jump to main.
* This function configures the external SRAM mounted on STM3210E-EVAL
* board (STM32 High density devices). This SRAM will be used as program
* data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
required, then adjust the Register Addresses */
/* Enable FSMC clock */
RCC->AHBENR = 0x00000114;
/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
RCC->APB2ENR = 0x000001E0;
/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
/*---------------- SRAM Address lines configuration -------------------------*/
/*---------------- NOE and NWE configuration --------------------------------*/
/*---------------- NE3 configuration ----------------------------------------*/
/*---------------- NBL0, NBL1 configuration ---------------------------------*/
GPIOD->CRL = 0x44BB44BB;
GPIOD->CRH = 0xBBBBBBBB;
GPIOE->CRL = 0xB44444BB;
GPIOE->CRH = 0xBBBBBBBB;
GPIOF->CRL = 0x44BBBBBB;
GPIOF->CRH = 0xBBBB4444;
GPIOG->CRL = 0x44BBBBBB;
GPIOG->CRH = 0x44444B44;
/*---------------- FSMC Configuration ---------------------------------------*/
/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
FSMC_Bank1->BTCR[4] = 0x00001011;
FSMC_Bank1->BTCR[5] = 0x00000200;
}
#endif /* DATA_IN_ExtSRAM */
#ifdef SYSCLK_FREQ_HSE
/**
* @brief Selects HSE as System clock source and configure HCLK, PCLK2
* and PCLK1 prescalers.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
static void SetSysClockToHSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 0 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
#ifndef STM32F10X_CL
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#else
if (HSE_VALUE <= 24000000)
{
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
}
else
{
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
}
#endif /* STM32F10X_CL */
#endif
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
/* Select HSE as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
/* Wait till HSE is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
#elif defined SYSCLK_FREQ_24MHz
/**
* @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
* and PCLK1 prescalers.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
static void SetSysClockTo24(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 0 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#endif
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
#ifdef STM32F10X_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL6);
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
/* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
#else
/* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
#endif /* STM32F10X_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
#elif defined SYSCLK_FREQ_36MHz
/**
* @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
* and PCLK1 prescalers.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
static void SetSysClockTo36(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
#ifdef STM32F10X_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL9);
/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}
#else
/* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
#endif /* STM32F10X_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
#elif defined SYSCLK_FREQ_48MHz
/**
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
* and PCLK1 prescalers.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
static void SetSysClockTo48(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
#ifdef STM32F10X_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}
/* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL6);
#else
/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
#endif /* STM32F10X_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
#elif defined SYSCLK_FREQ_56MHz
/**
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
* and PCLK1 prescalers.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
static void SetSysClockTo56(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 2 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
#ifdef STM32F10X_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}
/* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL7);
#else
/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
#endif /* STM32F10X_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
#elif defined SYSCLK_FREQ_72MHz
/**
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
* and PCLK1 prescalers.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
static void SetSysClockTo72(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 2 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
#ifdef STM32F10X_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}
/* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLMULL9);
#else
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
#endif /* STM32F10X_CL */
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
RTE/RTE_Components.h 0 → 100644
/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'MotorControl'
* Target: 'PWM'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#endif /* RTE_COMPONENTS_H */
main.c 0 → 100644
#include "step_motor.h"
#include "stm32f10x.h"
int main(void) {
// 初始化步进电机控制
StepperMotor_Init();
// 定义步进电机结构体
StepMotor motor = {
.stepcount = 0, // 初始步数
.direction = 1, // 初始方向（1：顺时针）
.curSpeed = 0, // 初始速度为0
.desSpeed = 0, // 目标速度
.maxSpeed = 9375, // 最大转速（假设值）
.speedStatus = SPEED_NONE, // 初始速度状态
.stepcountMode = 0, // 脉冲计数模式
.curlocation = 0, // 当前位置
.deslocation = 0, // 目标位置
.acceleration = 1000, // 加速度 (步/秒^2)
.deceleration = 1000, // 减速度 (步/秒^2)
.psc = 71, // 预分频器
.arr = 999 // 自动重装载寄存器
};
// 初始化定时器 TIM3
TIM3_Init(motor.psc, motor.arr);
// 设置初始方向（例如顺时针）
Set_Direction(motor.direction);
// 使能步进电机
Enable_Stepper(true);
// 主循环
while (1) {
// 例子：加速到目标速度
Update_Motor_Status(&motor, SPEED_ACC, 9375, 1000); // 以1000 RPM/s的加速度加速到9375 RPM
// 保持匀速一段时间
Delay(5000); // 延时5秒
// 例子：减速到停止
Update_Motor_Status(&motor, SPEED_DEC, 0, 1000); // 以1000 RPM/s的减速度减速到停止
// 保持停止一段时间
Delay(5000); // 延时5秒
}
}
\ No newline at end of file
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment